Commit 9710a5c1 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/dvo: Rename the "active data order" bits 



We have two sets of bits for DVO "data order" stuff. Rename
one set to ACT_DATA_ORDER to make it clear they are separate
bitfields.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221122120825.26338-7-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 5abd7d8d

drivers/gpu/drm/i915/display/intel_dvo.c

+2 −2
Original line number Diff line number Diff line
@@ -288,10 +288,10 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state, 
	enum pipe pipe = crtc->pipe;

	u32 dvo_val;



	/* Save the data order, since I don't know what it should be set to. */

	/* Save the active data order, since I don't know what it should be set to. */

	dvo_val = intel_de_read(i915, DVO(port)) &

		  (DVO_DEDICATED_INT_ENABLE |

		   DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);

		   DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_GBRG);

	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |

		   DVO_BLANK_ACTIVE_HIGH;

drivers/gpu/drm/i915/i915_reg.h

+4 −4
Original line number Diff line number Diff line
@@ -2613,10 +2613,10 @@ 
#define   DVO_VSYNC_TRISTATE		(1 << 9)

#define   DVO_HSYNC_TRISTATE		(1 << 8)

#define   DVO_BORDER_ENABLE		(1 << 7)

#define   DVO_DATA_ORDER_GBRG		(1 << 6)

#define   DVO_DATA_ORDER_RGGB		(0 << 6)

#define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)

#define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)

#define   DVO_ACT_DATA_ORDER_GBRG		(1 << 6)

#define   DVO_ACT_DATA_ORDER_RGGB		(0 << 6)

#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	(0 << 6)

#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	(1 << 6)

#define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)

#define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)

#define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)