Commit 96e9df33 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-5.15' of...

Merge tag 'phy-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next

Vinod writes:

phy-for-5.15

  - Updates:
        - Yaml conversion for Freescale imx8mq usb phy, TI AM654 SERDES phy,
          Cadence torrent phy
        - Updates for Amlogic Meson8b-usb2 phy, Samsung ufs phy

  - New support:
        - UFS phy for Qualcomm SM6115
	- PCIe & USB/DP phy for Qualcomm sc8180x
	- USB3 PHY support for Qualcomm IPQ6018
	- Renesas USB2.0 PHY for RZ/G2L

* tag 'phy-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (45 commits)
  phy: qcom-qmp: Add support for SM6115 UFS phy
  dt-bindings: phy: qcom,qmp: Add SM6115 UFS PHY bindings
  phy: qmp: Provide unique clock names for DP clocks
  phy: xilinx: zynqmp: skip PHY initialization and PLL lock for USB
  phy: amlogic: meson8b-usb2: don't log an error on -EPROBE_DEFER
  phy: amlogic: meson8b-usb2: Power off the PHY by putting it into reset mode
  phy: phy-mtk-mipi-dsi: convert to devm_platform_ioremap_resource
  phy: phy-mtk-mipi-dsi: remove dummy assignment of error number
  phy: phy-mtk-hdmi: convert to devm_platform_ioremap_resource
  phy: phy-mtk-ufs: use clock bulk to get clocks
  phy: phy-mtk-tphy: remove error log of ioremap failure
  phy: phy-mtk-tphy: print error log using child device
  phy: phy-mtk-tphy: support type switch by pericfg
  phy: phy-mtk-tphy: use clock bulk to get clocks
  dt-bindings: phy: mediatek: tphy: support type switch by pericfg
  phy: cadence-torrent: Check PIPE mode PHY status to be ready for operation
  phy: cadence-torrent: Add debug information for PHY configuration
  phy: cadence-torrent: Add separate functions for reusable code
  phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref clock
  phy: cadence-torrent: Add PHY registers for DP in array format
  ...
parents c446e40e 152a810e
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* Freescale i.MX8MQ USB3 PHY binding

Required properties:
- compatible:	Should be "fsl,imx8mq-usb-phy" or "fsl,imx8mp-usb-phy"
- #phys-cells:	must be 0 (see phy-bindings.txt in this directory)
- reg:		The base address and length of the registers
- clocks:	phandles to the clocks for each clock listed in clock-names
- clock-names:	must contain "phy"

Optional properties:
- vbus-supply: A phandle to the regulator for USB VBUS.

Example:
	usb3_phy0: phy@381f0040 {
		compatible = "fsl,imx8mq-usb-phy";
		reg = <0x381f0040 0x40>;
		clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
		clock-names = "phy";
		#phy-cells = <0>;
	};
+53 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8MQ USB3 PHY binding

maintainers:
  - Li Jun <jun.li@nxp.com>

properties:
  compatible:
    enum:
      - fsl,imx8mq-usb-phy
      - fsl,imx8mp-usb-phy

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: phy

  vbus-supply:
    description:
      A phandle to the regulator for USB VBUS.

required:
  - compatible
  - reg
  - "#phy-cells"
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mq-clock.h>
    usb3_phy0: phy@381f0040 {
        compatible = "fsl,imx8mq-usb-phy";
        reg = <0x381f0040 0x40>;
        clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
        clock-names = "phy";
        #phy-cells = <0>;
    };
+1 −1
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/intel,phy-keembay-usb.yaml#
$id: http://devicetree.org/schemas/phy/intel,keembay-phy-usb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Keem Bay USB PHY bindings
+25 −5
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@@ -15,7 +15,7 @@ description: |
  controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.

  Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
  T-PHY V2 (mt2712) when works on USB mode:
  T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
  -----------------------------------
  Version 1:
  port        offset    bank
@@ -34,7 +34,7 @@ description: |
  u2 port2    0x1800    U2PHY_COM
              ...

  Version 2:
  Version 2/3:
  port        offset    bank
  u2 port0    0x0000    MISC
              0x0100    FMREG
@@ -59,7 +59,8 @@ description: |

  SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
  into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
  added on V2.
  added on V2; the FMREG bank for slew rate calibration is not used anymore
  and reserved on V3;

properties:
  $nodename:
@@ -79,8 +80,11 @@ properties:
              - mediatek,mt2712-tphy
              - mediatek,mt7629-tphy
              - mediatek,mt8183-tphy
              - mediatek,mt8195-tphy
          - const: mediatek,generic-tphy-v2
      - items:
          - enum:
              - mediatek,mt8195-tphy
          - const: mediatek,generic-tphy-v3
      - const: mediatek,mt2701-u3phy
        deprecated: true
      - const: mediatek,mt2712-u3phy
@@ -91,7 +95,7 @@ properties:
    description:
      Register shared by multiple ports, exclude port's private register.
      It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
      T-PHY V2, such as mt2712.
      T-PHY V2/V3, such as mt2712.
    maxItems: 1

  "#address-cells":
@@ -197,6 +201,22 @@ patternProperties:
          Specify the flag to enable BC1.2 if support it
        type: boolean

      mediatek,syscon-type:
        $ref: /schemas/types.yaml#/definitions/phandle-array
        maxItems: 1
        description:
          A phandle to syscon used to access the register of type switch,
          the field should always be 3 cells long.
        items:
          items:
            - description:
                The first cell represents a phandle to syscon
            - description:
                The second cell represents the register offset
            - description:
                The third cell represents the index of config segment
              enum: [0, 1, 2, 3]

    required:
      - reg
      - "#phy-cells"
+4 −0
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@@ -18,6 +18,7 @@ properties:
  compatible:
    enum:
      - qcom,ipq6018-qmp-pcie-phy
      - qcom,ipq6018-qmp-usb3-phy
      - qcom,ipq8074-qmp-pcie-phy
      - qcom,ipq8074-qmp-usb3-phy
      - qcom,msm8996-qmp-pcie-phy
@@ -27,6 +28,7 @@ properties:
      - qcom,msm8998-qmp-ufs-phy
      - qcom,msm8998-qmp-usb3-phy
      - qcom,sc7180-qmp-usb3-phy
      - qcom,sc8180x-qmp-pcie-phy
      - qcom,sc8180x-qmp-ufs-phy
      - qcom,sc8180x-qmp-usb3-phy
      - qcom,sdm845-qhp-pcie-phy
@@ -34,6 +36,7 @@ properties:
      - qcom,sdm845-qmp-ufs-phy
      - qcom,sdm845-qmp-usb3-phy
      - qcom,sdm845-qmp-usb3-uni-phy
      - qcom,sm6115-qmp-ufs-phy
      - qcom,sm8150-qmp-ufs-phy
      - qcom,sm8150-qmp-usb3-phy
      - qcom,sm8150-qmp-usb3-uni-phy
@@ -326,6 +329,7 @@ allOf:
        compatible:
          contains:
            enum:
              - qcom,sc8180x-qmp-pcie-phy
              - qcom,sdm845-qhp-pcie-phy
              - qcom,sdm845-qmp-pcie-phy
              - qcom,sdx55-qmp-pcie-phy
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