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arm64: tlbflush: Rename MAX_TLBI_OPS
mainline inclusion from mainline-v6.7-rc1 commit ec1c3b9ff16082f880b304be40992568f4eee6a7 category: performance bugzilla: https://gitee.com/openeuler/kernel/issues/IB82FR CVE: NA ------------------------------------------------- Perhaps unsurprisingly, I-cache invalidations suffer from performance issues similar to TLB invalidations on certain systems. TLB and I-cache maintenance all result in DVM on the mesh, which is where the real bottleneck lies. Rename the heuristic to point the finger at DVM, such that it may be reused for limiting I-cache invalidations. Reviewed-by:Gavin Shan <gshan@redhat.com> Tested-by:
Gavin Shan <gshan@redhat.com> Acked-by:
Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20230920080133.944717-2-oliver.upton@linux.dev Signed-off-by:
Oliver Upton <oliver.upton@linux.dev> (cherry picked from commit ec1c3b9ff16082f880b304be40992568f4eee6a7) Signed-off-by:
Kefeng Wang <wangkefeng.wang@huawei.com>