Commit 96983ffe authored by Kevin Cernekee's avatar Kevin Cernekee Committed by Ralf Baechle
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MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines. 



This extends commit a8ca8b64 to cover
MIPSxx-style board cache code.

Signed-off-by: default avatarKevin Cernekee <cernekee@gmail.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent a648e811

arch/mips/mm/sc-mips.c

+5 −0
Original line number Diff line number Diff line
@@ -32,6 +32,11 @@ static void mips_sc_wback_inv(unsigned long addr, unsigned long size) 
 */

static void mips_sc_inv(unsigned long addr, unsigned long size)

{

	unsigned long lsize = cpu_scache_line_size();

	unsigned long almask = ~(lsize - 1);



	cache_op(Hit_Writeback_Inv_SD, addr & almask);

	cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);

	blast_inv_scache_range(addr, addr + size);

}