Commit 9651f00e authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/perf' into for-next/core 

* for-next/perf: (24 commits)
  KVM: arm64: Ensure CPU PMU probes before pKVM host de-privilege
  drivers/perf: hisi: add NULL check for name
  drivers/perf: hisi: Remove redundant initialized of pmu->name
  perf/arm-cmn: Fix port detection for CMN-700
  arm64: pmuv3: dynamically map PERF_COUNT_HW_BRANCH_INSTRUCTIONS
  perf/arm-cmn: Validate cycles events fully
  Revert "ARM: mach-virt: Select PMUv3 driver by default"
  drivers/perf: apple_m1: Add Apple M2 support
  dt-bindings: arm-pmu: Add PMU compatible strings for Apple M2 cores
  perf: arm_cspmu: Fix variable dereference warning
  perf/amlogic: Fix config1/config2 parsing issue
  drivers/perf: Use devm_platform_get_and_ioremap_resource()
  kbuild, drivers/perf: remove MODULE_LICENSE in non-modules
  perf: qcom: Use devm_platform_get_and_ioremap_resource()
  perf: arm: Use devm_platform_get_and_ioremap_resource()
  perf/arm-cmn: Move overlapping wp_combine field
  ARM: mach-virt: Select PMUv3 driver by default
  ARM: perf: Allow the use of the PMUv3 driver on 32bit ARM
  ARM: Make CONFIG_CPU_V7 valid for 32bit ARMv8 implementations
  perf: pmuv3: Change GENMASK to GENMASK_ULL
  ...
parents 1bb31cc7 87727ba2

Documentation/devicetree/bindings/arm/pmu.yaml

+2 −0
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ properties: 
    items:

      - enum:

          - apm,potenza-pmu

          - apple,avalanche-pmu

          - apple,blizzard-pmu

          - apple,firestorm-pmu

          - apple,icestorm-pmu

          - arm,armv8-pmuv3 # Only for s/w models

arch/arm/include/asm/arm_pmuv3.h

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+247 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2012 ARM Ltd.

 */



#ifndef __ASM_PMUV3_H

#define __ASM_PMUV3_H



#include <asm/cp15.h>

#include <asm/cputype.h>



#define PMCCNTR			__ACCESS_CP15_64(0, c9)



#define PMCR			__ACCESS_CP15(c9,  0, c12, 0)

#define PMCNTENSET		__ACCESS_CP15(c9,  0, c12, 1)

#define PMCNTENCLR		__ACCESS_CP15(c9,  0, c12, 2)

#define PMOVSR			__ACCESS_CP15(c9,  0, c12, 3)

#define PMSELR			__ACCESS_CP15(c9,  0, c12, 5)

#define PMCEID0			__ACCESS_CP15(c9,  0, c12, 6)

#define PMCEID1			__ACCESS_CP15(c9,  0, c12, 7)

#define PMXEVTYPER		__ACCESS_CP15(c9,  0, c13, 1)

#define PMXEVCNTR		__ACCESS_CP15(c9,  0, c13, 2)

#define PMUSERENR		__ACCESS_CP15(c9,  0, c14, 0)

#define PMINTENSET		__ACCESS_CP15(c9,  0, c14, 1)

#define PMINTENCLR		__ACCESS_CP15(c9,  0, c14, 2)

#define PMMIR			__ACCESS_CP15(c9,  0, c14, 6)

#define PMCCFILTR		__ACCESS_CP15(c14, 0, c15, 7)



#define PMEVCNTR0		__ACCESS_CP15(c14, 0, c8, 0)

#define PMEVCNTR1		__ACCESS_CP15(c14, 0, c8, 1)

#define PMEVCNTR2		__ACCESS_CP15(c14, 0, c8, 2)

#define PMEVCNTR3		__ACCESS_CP15(c14, 0, c8, 3)

#define PMEVCNTR4		__ACCESS_CP15(c14, 0, c8, 4)

#define PMEVCNTR5		__ACCESS_CP15(c14, 0, c8, 5)

#define PMEVCNTR6		__ACCESS_CP15(c14, 0, c8, 6)

#define PMEVCNTR7		__ACCESS_CP15(c14, 0, c8, 7)

#define PMEVCNTR8		__ACCESS_CP15(c14, 0, c9, 0)

#define PMEVCNTR9		__ACCESS_CP15(c14, 0, c9, 1)

#define PMEVCNTR10		__ACCESS_CP15(c14, 0, c9, 2)

#define PMEVCNTR11		__ACCESS_CP15(c14, 0, c9, 3)

#define PMEVCNTR12		__ACCESS_CP15(c14, 0, c9, 4)

#define PMEVCNTR13		__ACCESS_CP15(c14, 0, c9, 5)

#define PMEVCNTR14		__ACCESS_CP15(c14, 0, c9, 6)

#define PMEVCNTR15		__ACCESS_CP15(c14, 0, c9, 7)

#define PMEVCNTR16		__ACCESS_CP15(c14, 0, c10, 0)

#define PMEVCNTR17		__ACCESS_CP15(c14, 0, c10, 1)

#define PMEVCNTR18		__ACCESS_CP15(c14, 0, c10, 2)

#define PMEVCNTR19		__ACCESS_CP15(c14, 0, c10, 3)

#define PMEVCNTR20		__ACCESS_CP15(c14, 0, c10, 4)

#define PMEVCNTR21		__ACCESS_CP15(c14, 0, c10, 5)

#define PMEVCNTR22		__ACCESS_CP15(c14, 0, c10, 6)

#define PMEVCNTR23		__ACCESS_CP15(c14, 0, c10, 7)

#define PMEVCNTR24		__ACCESS_CP15(c14, 0, c11, 0)

#define PMEVCNTR25		__ACCESS_CP15(c14, 0, c11, 1)

#define PMEVCNTR26		__ACCESS_CP15(c14, 0, c11, 2)

#define PMEVCNTR27		__ACCESS_CP15(c14, 0, c11, 3)

#define PMEVCNTR28		__ACCESS_CP15(c14, 0, c11, 4)

#define PMEVCNTR29		__ACCESS_CP15(c14, 0, c11, 5)

#define PMEVCNTR30		__ACCESS_CP15(c14, 0, c11, 6)



#define PMEVTYPER0		__ACCESS_CP15(c14, 0, c12, 0)

#define PMEVTYPER1		__ACCESS_CP15(c14, 0, c12, 1)

#define PMEVTYPER2		__ACCESS_CP15(c14, 0, c12, 2)

#define PMEVTYPER3		__ACCESS_CP15(c14, 0, c12, 3)

#define PMEVTYPER4		__ACCESS_CP15(c14, 0, c12, 4)

#define PMEVTYPER5		__ACCESS_CP15(c14, 0, c12, 5)

#define PMEVTYPER6		__ACCESS_CP15(c14, 0, c12, 6)

#define PMEVTYPER7		__ACCESS_CP15(c14, 0, c12, 7)

#define PMEVTYPER8		__ACCESS_CP15(c14, 0, c13, 0)

#define PMEVTYPER9		__ACCESS_CP15(c14, 0, c13, 1)

#define PMEVTYPER10		__ACCESS_CP15(c14, 0, c13, 2)

#define PMEVTYPER11		__ACCESS_CP15(c14, 0, c13, 3)

#define PMEVTYPER12		__ACCESS_CP15(c14, 0, c13, 4)

#define PMEVTYPER13		__ACCESS_CP15(c14, 0, c13, 5)

#define PMEVTYPER14		__ACCESS_CP15(c14, 0, c13, 6)

#define PMEVTYPER15		__ACCESS_CP15(c14, 0, c13, 7)

#define PMEVTYPER16		__ACCESS_CP15(c14, 0, c14, 0)

#define PMEVTYPER17		__ACCESS_CP15(c14, 0, c14, 1)

#define PMEVTYPER18		__ACCESS_CP15(c14, 0, c14, 2)

#define PMEVTYPER19		__ACCESS_CP15(c14, 0, c14, 3)

#define PMEVTYPER20		__ACCESS_CP15(c14, 0, c14, 4)

#define PMEVTYPER21		__ACCESS_CP15(c14, 0, c14, 5)

#define PMEVTYPER22		__ACCESS_CP15(c14, 0, c14, 6)

#define PMEVTYPER23		__ACCESS_CP15(c14, 0, c14, 7)

#define PMEVTYPER24		__ACCESS_CP15(c14, 0, c15, 0)

#define PMEVTYPER25		__ACCESS_CP15(c14, 0, c15, 1)

#define PMEVTYPER26		__ACCESS_CP15(c14, 0, c15, 2)

#define PMEVTYPER27		__ACCESS_CP15(c14, 0, c15, 3)

#define PMEVTYPER28		__ACCESS_CP15(c14, 0, c15, 4)

#define PMEVTYPER29		__ACCESS_CP15(c14, 0, c15, 5)

#define PMEVTYPER30		__ACCESS_CP15(c14, 0, c15, 6)



#define RETURN_READ_PMEVCNTRN(n) \

	return read_sysreg(PMEVCNTR##n)

static unsigned long read_pmevcntrn(int n)

{

	PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);

	return 0;

}



#define WRITE_PMEVCNTRN(n) \

	write_sysreg(val, PMEVCNTR##n)

static void write_pmevcntrn(int n, unsigned long val)

{

	PMEVN_SWITCH(n, WRITE_PMEVCNTRN);

}



#define WRITE_PMEVTYPERN(n) \

	write_sysreg(val, PMEVTYPER##n)

static void write_pmevtypern(int n, unsigned long val)

{

	PMEVN_SWITCH(n, WRITE_PMEVTYPERN);

}



static inline unsigned long read_pmmir(void)

{

	return read_sysreg(PMMIR);

}



static inline u32 read_pmuver(void)

{

	/* PMUVers is not a signed field */

	u32 dfr0 = read_cpuid_ext(CPUID_EXT_DFR0);



	return (dfr0 >> 24) & 0xf;

}



static inline void write_pmcr(u32 val)

{

	write_sysreg(val, PMCR);

}



static inline u32 read_pmcr(void)

{

	return read_sysreg(PMCR);

}



static inline void write_pmselr(u32 val)

{

	write_sysreg(val, PMSELR);

}



static inline void write_pmccntr(u64 val)

{

	write_sysreg(val, PMCCNTR);

}



static inline u64 read_pmccntr(void)

{

	return read_sysreg(PMCCNTR);

}



static inline void write_pmxevcntr(u32 val)

{

	write_sysreg(val, PMXEVCNTR);

}



static inline u32 read_pmxevcntr(void)

{

	return read_sysreg(PMXEVCNTR);

}



static inline void write_pmxevtyper(u32 val)

{

	write_sysreg(val, PMXEVTYPER);

}



static inline void write_pmcntenset(u32 val)

{

	write_sysreg(val, PMCNTENSET);

}



static inline void write_pmcntenclr(u32 val)

{

	write_sysreg(val, PMCNTENCLR);

}



static inline void write_pmintenset(u32 val)

{

	write_sysreg(val, PMINTENSET);

}



static inline void write_pmintenclr(u32 val)

{

	write_sysreg(val, PMINTENCLR);

}



static inline void write_pmccfiltr(u32 val)

{

	write_sysreg(val, PMCCFILTR);

}



static inline void write_pmovsclr(u32 val)

{

	write_sysreg(val, PMOVSR);

}



static inline u32 read_pmovsclr(void)

{

	return read_sysreg(PMOVSR);

}



static inline void write_pmuserenr(u32 val)

{

	write_sysreg(val, PMUSERENR);

}



static inline u32 read_pmceid0(void)

{

	return read_sysreg(PMCEID0);

}



static inline u32 read_pmceid1(void)

{

	return read_sysreg(PMCEID1);

}



static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}

static inline void kvm_clr_pmu_events(u32 clr) {}

static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)

{

	return false;

}



/* PMU Version in DFR Register */

#define ARMV8_PMU_DFR_VER_NI        0

#define ARMV8_PMU_DFR_VER_V3P4      0x5

#define ARMV8_PMU_DFR_VER_V3P5      0x6

#define ARMV8_PMU_DFR_VER_IMP_DEF   0xF



static inline bool pmuv3_implemented(int pmuver)

{

	return !(pmuver == ARMV8_PMU_DFR_VER_IMP_DEF ||

		 pmuver == ARMV8_PMU_DFR_VER_NI);

}



static inline bool is_pmuv3p4(int pmuver)

{

	return pmuver >= ARMV8_PMU_DFR_VER_V3P4;

}



static inline bool is_pmuv3p5(int pmuver)

{

	return pmuver >= ARMV8_PMU_DFR_VER_V3P5;

}



#endif

arch/arm/mm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -403,7 +403,7 @@ config CPU_V6K 
	select CPU_THUMB_CAPABLE

	select CPU_TLB_V6 if MMU



# ARMv7

# ARMv7 and ARMv8 architectures

config CPU_V7

	bool

	select CPU_32v6K

arch/arm64/include/asm/arm_pmuv3.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2012 ARM Ltd.

 */



#ifndef __ASM_PMUV3_H

#define __ASM_PMUV3_H



#include <linux/kvm_host.h>



#include <asm/cpufeature.h>

#include <asm/sysreg.h>



#define RETURN_READ_PMEVCNTRN(n) \

	return read_sysreg(pmevcntr##n##_el0)

static unsigned long read_pmevcntrn(int n)

{

	PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);

	return 0;

}



#define WRITE_PMEVCNTRN(n) \

	write_sysreg(val, pmevcntr##n##_el0)

static void write_pmevcntrn(int n, unsigned long val)

{

	PMEVN_SWITCH(n, WRITE_PMEVCNTRN);

}



#define WRITE_PMEVTYPERN(n) \

	write_sysreg(val, pmevtyper##n##_el0)

static void write_pmevtypern(int n, unsigned long val)

{

	PMEVN_SWITCH(n, WRITE_PMEVTYPERN);

}



static inline unsigned long read_pmmir(void)

{

	return read_cpuid(PMMIR_EL1);

}



static inline u32 read_pmuver(void)

{

	u64 dfr0 = read_sysreg(id_aa64dfr0_el1);



	return cpuid_feature_extract_unsigned_field(dfr0,

			ID_AA64DFR0_EL1_PMUVer_SHIFT);

}



static inline void write_pmcr(u32 val)

{

	write_sysreg(val, pmcr_el0);

}



static inline u32 read_pmcr(void)

{

	return read_sysreg(pmcr_el0);

}



static inline void write_pmselr(u32 val)

{

	write_sysreg(val, pmselr_el0);

}



static inline void write_pmccntr(u64 val)

{

	write_sysreg(val, pmccntr_el0);

}



static inline u64 read_pmccntr(void)

{

	return read_sysreg(pmccntr_el0);

}



static inline void write_pmxevcntr(u32 val)

{

	write_sysreg(val, pmxevcntr_el0);

}



static inline u32 read_pmxevcntr(void)

{

	return read_sysreg(pmxevcntr_el0);

}



static inline void write_pmxevtyper(u32 val)

{

	write_sysreg(val, pmxevtyper_el0);

}



static inline void write_pmcntenset(u32 val)

{

	write_sysreg(val, pmcntenset_el0);

}



static inline void write_pmcntenclr(u32 val)

{

	write_sysreg(val, pmcntenclr_el0);

}



static inline void write_pmintenset(u32 val)

{

	write_sysreg(val, pmintenset_el1);

}



static inline void write_pmintenclr(u32 val)

{

	write_sysreg(val, pmintenclr_el1);

}



static inline void write_pmccfiltr(u32 val)

{

	write_sysreg(val, pmccfiltr_el0);

}



static inline void write_pmovsclr(u32 val)

{

	write_sysreg(val, pmovsclr_el0);

}



static inline u32 read_pmovsclr(void)

{

	return read_sysreg(pmovsclr_el0);

}



static inline void write_pmuserenr(u32 val)

{

	write_sysreg(val, pmuserenr_el0);

}



static inline u32 read_pmceid0(void)

{

	return read_sysreg(pmceid0_el0);

}



static inline u32 read_pmceid1(void)

{

	return read_sysreg(pmceid1_el0);

}



static inline bool pmuv3_implemented(int pmuver)

{

	return !(pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF ||

		 pmuver == ID_AA64DFR0_EL1_PMUVer_NI);

}



static inline bool is_pmuv3p4(int pmuver)

{

	return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4;

}



static inline bool is_pmuv3p5(int pmuver)

{

	return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5;

}



#endif

arch/arm64/include/asm/perf_event.h

+0 −249
Original line number Diff line number Diff line
@@ -9,255 +9,6 @@ 
#include <asm/stack_pointer.h>

#include <asm/ptrace.h>



#define	ARMV8_PMU_MAX_COUNTERS	32

#define	ARMV8_PMU_COUNTER_MASK	(ARMV8_PMU_MAX_COUNTERS - 1)



/*

 * Common architectural and microarchitectural event numbers.

 */

#define ARMV8_PMUV3_PERFCTR_SW_INCR				0x0000

#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL			0x0001

#define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL			0x0002

#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL			0x0003

#define ARMV8_PMUV3_PERFCTR_L1D_CACHE				0x0004

#define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL			0x0005

#define ARMV8_PMUV3_PERFCTR_LD_RETIRED				0x0006

#define ARMV8_PMUV3_PERFCTR_ST_RETIRED				0x0007

#define ARMV8_PMUV3_PERFCTR_INST_RETIRED			0x0008

#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN				0x0009

#define ARMV8_PMUV3_PERFCTR_EXC_RETURN				0x000A

#define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED			0x000B

#define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED			0x000C

#define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED			0x000D

#define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED			0x000E

#define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED		0x000F

#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED				0x0010

#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES				0x0011

#define ARMV8_PMUV3_PERFCTR_BR_PRED				0x0012

#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS				0x0013

#define ARMV8_PMUV3_PERFCTR_L1I_CACHE				0x0014

#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB			0x0015

#define ARMV8_PMUV3_PERFCTR_L2D_CACHE				0x0016

#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL			0x0017

#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB			0x0018

#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS				0x0019

#define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR			0x001A

#define ARMV8_PMUV3_PERFCTR_INST_SPEC				0x001B

#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED			0x001C

#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES				0x001D

#define ARMV8_PMUV3_PERFCTR_CHAIN				0x001E

#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE			0x001F

#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE			0x0020

#define ARMV8_PMUV3_PERFCTR_BR_RETIRED				0x0021

#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED			0x0022

#define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND			0x0023

#define ARMV8_PMUV3_PERFCTR_STALL_BACKEND			0x0024

#define ARMV8_PMUV3_PERFCTR_L1D_TLB				0x0025

#define ARMV8_PMUV3_PERFCTR_L1I_TLB				0x0026

#define ARMV8_PMUV3_PERFCTR_L2I_CACHE				0x0027

#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL			0x0028

#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE			0x0029

#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL			0x002A

#define ARMV8_PMUV3_PERFCTR_L3D_CACHE				0x002B

#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB			0x002C

#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL			0x002D

#define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL			0x002E

#define ARMV8_PMUV3_PERFCTR_L2D_TLB				0x002F

#define ARMV8_PMUV3_PERFCTR_L2I_TLB				0x0030

#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS			0x0031

#define ARMV8_PMUV3_PERFCTR_LL_CACHE				0x0032

#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS			0x0033

#define ARMV8_PMUV3_PERFCTR_DTLB_WALK				0x0034

#define ARMV8_PMUV3_PERFCTR_ITLB_WALK				0x0035

#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD				0x0036

#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD			0x0037

#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD			0x0038

#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD			0x0039

#define ARMV8_PMUV3_PERFCTR_OP_RETIRED				0x003A

#define ARMV8_PMUV3_PERFCTR_OP_SPEC				0x003B

#define ARMV8_PMUV3_PERFCTR_STALL				0x003C

#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND			0x003D

#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND			0x003E

#define ARMV8_PMUV3_PERFCTR_STALL_SLOT				0x003F



/* Statistical profiling extension microarchitectural events */

#define	ARMV8_SPE_PERFCTR_SAMPLE_POP				0x4000

#define	ARMV8_SPE_PERFCTR_SAMPLE_FEED				0x4001

#define	ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE			0x4002

#define	ARMV8_SPE_PERFCTR_SAMPLE_COLLISION			0x4003



/* AMUv1 architecture events */

#define	ARMV8_AMU_PERFCTR_CNT_CYCLES				0x4004

#define	ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM			0x4005



/* long-latency read miss events */

#define	ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS			0x4006

#define	ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD			0x4009

#define	ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS			0x400A

#define	ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD			0x400B



/* Trace buffer events */

#define ARMV8_PMUV3_PERFCTR_TRB_WRAP				0x400C

#define ARMV8_PMUV3_PERFCTR_TRB_TRIG				0x400E



/* Trace unit events */

#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT0				0x4010

#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT1				0x4011

#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT2				0x4012

#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT3				0x4013

#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4			0x4018

#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5			0x4019

#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6			0x401A

#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7			0x401B



/* additional latency from alignment events */

#define	ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT			0x4020

#define	ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT			0x4021

#define	ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT			0x4022



/* Armv8.5 Memory Tagging Extension events */

#define	ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED			0x4024

#define	ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD			0x4025

#define	ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR			0x4026



/* ARMv8 recommended implementation defined event types */

#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD			0x0040

#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR			0x0041

#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD		0x0042

#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR		0x0043

#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER		0x0044

#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER		0x0045

#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM		0x0046

#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN			0x0047

#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL			0x0048



#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD			0x004C

#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR			0x004D

#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD				0x004E

#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR				0x004F

#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD			0x0050

#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR			0x0051

#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD		0x0052

#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR		0x0053



#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM		0x0056

#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN			0x0057

#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL			0x0058



#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD			0x005C

#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR			0x005D

#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD				0x005E

#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR				0x005F

#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD			0x0060

#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR			0x0061

#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED			0x0062

#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED		0x0063

#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL			0x0064

#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH			0x0065

#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD			0x0066

#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR			0x0067

#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC			0x0068

#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC			0x0069

#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC		0x006A



#define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC				0x006C

#define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC			0x006D

#define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC			0x006E

#define ARMV8_IMPDEF_PERFCTR_STREX_SPEC				0x006F

#define ARMV8_IMPDEF_PERFCTR_LD_SPEC				0x0070

#define ARMV8_IMPDEF_PERFCTR_ST_SPEC				0x0071

#define ARMV8_IMPDEF_PERFCTR_LDST_SPEC				0x0072

#define ARMV8_IMPDEF_PERFCTR_DP_SPEC				0x0073

#define ARMV8_IMPDEF_PERFCTR_ASE_SPEC				0x0074

#define ARMV8_IMPDEF_PERFCTR_VFP_SPEC				0x0075

#define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC			0x0076

#define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC			0x0077

#define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC			0x0078

#define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC			0x0079

#define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC			0x007A



#define ARMV8_IMPDEF_PERFCTR_ISB_SPEC				0x007C

#define ARMV8_IMPDEF_PERFCTR_DSB_SPEC				0x007D

#define ARMV8_IMPDEF_PERFCTR_DMB_SPEC				0x007E



#define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF				0x0081

#define ARMV8_IMPDEF_PERFCTR_EXC_SVC				0x0082

#define ARMV8_IMPDEF_PERFCTR_EXC_PABORT				0x0083

#define ARMV8_IMPDEF_PERFCTR_EXC_DABORT				0x0084



#define ARMV8_IMPDEF_PERFCTR_EXC_IRQ				0x0086

#define ARMV8_IMPDEF_PERFCTR_EXC_FIQ				0x0087

#define ARMV8_IMPDEF_PERFCTR_EXC_SMC				0x0088



#define ARMV8_IMPDEF_PERFCTR_EXC_HVC				0x008A

#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT			0x008B

#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT			0x008C

#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER			0x008D

#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ			0x008E

#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ			0x008F

#define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC				0x0090

#define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC				0x0091



#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD			0x00A0

#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR			0x00A1

#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD		0x00A2

#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR		0x00A3



#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM		0x00A6

#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN			0x00A7

#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL			0x00A8



/*

 * Per-CPU PMCR: config reg

 */

#define ARMV8_PMU_PMCR_E	(1 << 0) /* Enable all counters */

#define ARMV8_PMU_PMCR_P	(1 << 1) /* Reset all counters */

#define ARMV8_PMU_PMCR_C	(1 << 2) /* Cycle counter reset */

#define ARMV8_PMU_PMCR_D	(1 << 3) /* CCNT counts every 64th cpu cycle */

#define ARMV8_PMU_PMCR_X	(1 << 4) /* Export to ETM */

#define ARMV8_PMU_PMCR_DP	(1 << 5) /* Disable CCNT if non-invasive debug*/

#define ARMV8_PMU_PMCR_LC	(1 << 6) /* Overflow on 64 bit cycle counter */

#define ARMV8_PMU_PMCR_LP	(1 << 7) /* Long event counter enable */

#define	ARMV8_PMU_PMCR_N_SHIFT	11	 /* Number of counters supported */

#define	ARMV8_PMU_PMCR_N_MASK	0x1f

#define	ARMV8_PMU_PMCR_MASK	0xff	 /* Mask for writable bits */



/*

 * PMOVSR: counters overflow flag status reg

 */

#define	ARMV8_PMU_OVSR_MASK		0xffffffff	/* Mask for writable bits */

#define	ARMV8_PMU_OVERFLOWED_MASK	ARMV8_PMU_OVSR_MASK



/*

 * PMXEVTYPER: Event selection reg

 */

#define	ARMV8_PMU_EVTYPE_MASK	0xc800ffff	/* Mask for writable bits */

#define	ARMV8_PMU_EVTYPE_EVENT	0xffff		/* Mask for EVENT bits */



/*

 * Event filters for PMUv3

 */

#define	ARMV8_PMU_EXCLUDE_EL1	(1U << 31)

#define	ARMV8_PMU_EXCLUDE_EL0	(1U << 30)

#define	ARMV8_PMU_INCLUDE_EL2	(1U << 27)



/*

 * PMUSERENR: user enable reg

 */

#define ARMV8_PMU_USERENR_MASK	0xf		/* Mask for writable bits */

#define ARMV8_PMU_USERENR_EN	(1 << 0) /* PMU regs can be accessed at EL0 */

#define ARMV8_PMU_USERENR_SW	(1 << 1) /* PMSWINC can be written at EL0 */

#define ARMV8_PMU_USERENR_CR	(1 << 2) /* Cycle counter can be read at EL0 */

#define ARMV8_PMU_USERENR_ER	(1 << 3) /* Event counter can be read at EL0 */



/* PMMIR_EL1.SLOTS mask */

#define ARMV8_PMU_SLOTS_MASK	0xff



#define ARMV8_PMU_BUS_SLOTS_SHIFT 8

#define ARMV8_PMU_BUS_SLOTS_MASK 0xff

#define ARMV8_PMU_BUS_WIDTH_SHIFT 16

#define ARMV8_PMU_BUS_WIDTH_MASK 0xf



#ifdef CONFIG_PERF_EVENTS

struct pt_regs;

extern unsigned long perf_instruction_pointer(struct pt_regs *regs);