Unverified Commit 9645ccc7 authored by Nikita Shubin's avatar Nikita Shubin Committed by Arnd Bergmann
Browse files

ep93xx: clock: convert in-place to COMMON_CLK 



Converted in-place without moving file to drivers/clk.

tested on ts7250 (EP9302).

Only setting rate and change parent tested for, as they
are missing on ts7250:
- video
- I2S
- ADC/KEYPAD
- PWM

Only video and I2S clock are interesting, as they are
GATE + double DIV + MUX, all other are pretty much
common but require ep93xx_syscon_swlocked_write to set
registers.

Signed-off-by: default avatarNikita Shubin <nikita.shubin@maquefel.me>
Signed-off-by: default avatarAlexander Sverdlin <alexander.sverdlin@gmail.com>
Tested-by: default avatarAlexander Sverdlin <alexander.sverdlin@gmail.com>
Acked-by: default avatarAlexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20211018103105.146380-3-alexander.sverdlin@gmail.com

'
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent f4ff6b56

arch/arm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -347,7 +347,7 @@ config ARCH_EP93XX 
	select CLKSRC_MMIO

	select CPU_ARM920T

	select GPIOLIB

	select HAVE_LEGACY_CLK

	select COMMON_CLK

	help

	  This enables support for the Cirrus EP93xx series of CPUs.

arch/arm/mach-ep93xx/clock.c

+558 −417

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-ep93xx/core.c

+1 −1
Original line number Diff line number Diff line
@@ -214,7 +214,7 @@ static int ep93xx_ohci_power_on(struct platform_device *pdev) 
			return PTR_ERR(ep93xx_ohci_host_clock);

	}



	return clk_enable(ep93xx_ohci_host_clock);

	return clk_prepare_enable(ep93xx_ohci_host_clock);

}



static void ep93xx_ohci_power_off(struct platform_device *pdev)

arch/arm/mach-ep93xx/soc.h

+21 −21
Original line number Diff line number Diff line
@@ -111,19 +111,19 @@ 
#define EP93XX_SYSCON_PWRCNT		EP93XX_SYSCON_REG(0x04)

#define EP93XX_SYSCON_PWRCNT_FIR_EN	(1<<31)

#define EP93XX_SYSCON_PWRCNT_UARTBAUD	(1<<29)

#define EP93XX_SYSCON_PWRCNT_USH_EN	(1<<28)

#define EP93XX_SYSCON_PWRCNT_DMA_M2M1	(1<<27)

#define EP93XX_SYSCON_PWRCNT_DMA_M2M0	(1<<26)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P8	(1<<25)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P9	(1<<24)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P6	(1<<23)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P7	(1<<22)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P4	(1<<21)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P5	(1<<20)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P2	(1<<19)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P3	(1<<18)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P0	(1<<17)

#define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)

#define EP93XX_SYSCON_PWRCNT_USH_EN	28

#define EP93XX_SYSCON_PWRCNT_DMA_M2M1	27

#define EP93XX_SYSCON_PWRCNT_DMA_M2M0	26

#define EP93XX_SYSCON_PWRCNT_DMA_M2P8	25

#define EP93XX_SYSCON_PWRCNT_DMA_M2P9	24

#define EP93XX_SYSCON_PWRCNT_DMA_M2P6	23

#define EP93XX_SYSCON_PWRCNT_DMA_M2P7	22

#define EP93XX_SYSCON_PWRCNT_DMA_M2P4	21

#define EP93XX_SYSCON_PWRCNT_DMA_M2P5	20

#define EP93XX_SYSCON_PWRCNT_DMA_M2P2	19

#define EP93XX_SYSCON_PWRCNT_DMA_M2P3	18

#define EP93XX_SYSCON_PWRCNT_DMA_M2P0	17

#define EP93XX_SYSCON_PWRCNT_DMA_M2P1	16

#define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)

#define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)

#define EP93XX_SYSCON_CLKSET1		EP93XX_SYSCON_REG(0x20)
@@ -139,13 +139,13 @@ 
#define EP93XX_SYSCON_DEVCFG_GONK	(1<<27)

#define EP93XX_SYSCON_DEVCFG_TONG	(1<<26)

#define EP93XX_SYSCON_DEVCFG_MONG	(1<<25)

#define EP93XX_SYSCON_DEVCFG_U3EN	(1<<24)

#define EP93XX_SYSCON_DEVCFG_U3EN	24

#define EP93XX_SYSCON_DEVCFG_CPENA	(1<<23)

#define EP93XX_SYSCON_DEVCFG_A2ONG	(1<<22)

#define EP93XX_SYSCON_DEVCFG_A1ONG	(1<<21)

#define EP93XX_SYSCON_DEVCFG_U2EN	(1<<20)

#define EP93XX_SYSCON_DEVCFG_U2EN	20

#define EP93XX_SYSCON_DEVCFG_EXVC	(1<<19)

#define EP93XX_SYSCON_DEVCFG_U1EN	(1<<18)

#define EP93XX_SYSCON_DEVCFG_U1EN	18

#define EP93XX_SYSCON_DEVCFG_TIN	(1<<17)

#define EP93XX_SYSCON_DEVCFG_HC3IN	(1<<15)

#define EP93XX_SYSCON_DEVCFG_HC3EN	(1<<14)
@@ -163,12 +163,12 @@ 
#define EP93XX_SYSCON_DEVCFG_KEYS	(1<<1)

#define EP93XX_SYSCON_DEVCFG_SHENA	(1<<0)

#define EP93XX_SYSCON_VIDCLKDIV		EP93XX_SYSCON_REG(0x84)

#define EP93XX_SYSCON_CLKDIV_ENABLE	(1<<15)

#define EP93XX_SYSCON_CLKDIV_ENABLE	15

#define EP93XX_SYSCON_CLKDIV_ESEL	(1<<14)

#define EP93XX_SYSCON_CLKDIV_PSEL	(1<<13)

#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT	8

#define EP93XX_SYSCON_I2SCLKDIV		EP93XX_SYSCON_REG(0x8c)

#define EP93XX_SYSCON_I2SCLKDIV_SENA	(1<<31)

#define EP93XX_SYSCON_I2SCLKDIV_SENA	31

#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)

#define EP93XX_SYSCON_I2SCLKDIV_SPOL	(1<<19)

#define EP93XX_I2SCLKDIV_SDIV		(1 << 16)
@@ -177,9 +177,9 @@ 
#define EP93XX_I2SCLKDIV_LRDIV128	(2 << 17)

#define EP93XX_I2SCLKDIV_LRDIV_MASK	(3 << 17)

#define EP93XX_SYSCON_KEYTCHCLKDIV	EP93XX_SYSCON_REG(0x90)

#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	(1<<31)

#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	(1<<16)

#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN	(1<<15)

#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	31

#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	16

#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN	15

#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV	(1<<0)

#define EP93XX_SYSCON_SYSCFG		EP93XX_SYSCON_REG(0x9c)

#define EP93XX_SYSCON_SYSCFG_REV_MASK	(0xf0000000)