Unverified Commit 95f196f3 authored by Zong Li's avatar Zong Li Committed by Palmer Dabbelt
Browse files

soc: sifive: ccache: determine the cache level from dts 



Composable cache could be L2 or L3 cache, use 'cache-level' property of
device node to determine the level.

Signed-off-by: default avatarZong Li <zong.li@sifive.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220913061817.22564-4-zong.li@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent ca120a79

drivers/soc/sifive/sifive_ccache.c

+5 −1
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 
static void __iomem *ccache_base;

static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];

static struct riscv_cacheinfo_ops ccache_cache_ops;

static int level;



enum {

	DIR_CORR = 0,
@@ -144,7 +145,7 @@ static const struct attribute_group *ccache_get_priv_group(struct cacheinfo 
							   *this_leaf)

{

	/* We want to use private group for composable cache only */

	if (this_leaf->level == 2)

	if (this_leaf->level == level)

		return &priv_attr_group;

	else

		return NULL;
@@ -215,6 +216,9 @@ static int __init sifive_ccache_init(void) 
	if (!ccache_base)

		return -ENOMEM;



	if (of_property_read_u32(np, "cache-level", &level))

		return -ENOENT;



	intr_num = of_property_count_u32_elems(np, "interrupts");

	if (!intr_num) {

		pr_err("CCACHE: no interrupts property\n");