Commit 95bf2e60 authored by Wenhui Fan's avatar Wenhui Fan
Browse files

perf/x86/uncore: Correct the L3 PMU config for Hygon processors 

hygon inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IBCQ50


CVE: NA

---------------------------

The hwc->config is set in the function amd_uncore_l3_event_init() and not
use the return value of the function l3_thread_slice_mask() since commit
e6e832e8 ("perf/x86/amd/uncore: Refactor uncore management").

So adjust the code for Hygon, otherwise it will not set the L3 PMU config
correctly and cause #PF when using perf tool to monitor performance on
Hygon platforms.

Fixes: 26559114 ("perf/x86/uncore: Add L3 PMU support for Hygon family 18h model 6h")
Signed-off-by: default avatarWenhui Fan <fanwh@hygon.cn>
parent c949b128

arch/x86/events/amd/uncore.c

+2 −2
Original line number Diff line number Diff line
@@ -790,10 +790,10 @@ static int amd_uncore_l3_event_init(struct perf_event *event) 
	else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&

		 boot_cpu_data.x86 == 0x18) {

		if (boot_cpu_data.x86_model >= 0x6 && boot_cpu_data.x86_model <= 0xf)

			return ((config & HYGON_L3_SLICE_MASK) ? : HYGON_L3_SLICE_MASK) |

			mask = ((config & HYGON_L3_SLICE_MASK) ? : HYGON_L3_SLICE_MASK) |

			       ((config & HYGON_L3_THREAD_MASK) ? : HYGON_L3_THREAD_MASK);

		else

			return ((config & AMD64_L3_SLICE_MASK) ? : AMD64_L3_SLICE_MASK) |

			mask = ((config & AMD64_L3_SLICE_MASK) ? : AMD64_L3_SLICE_MASK) |

			       ((config & AMD64_L3_THREAD_MASK) ? : AMD64_L3_THREAD_MASK);

	}