Commit 95b1f6db authored Sep 06, 2020 by Paul Cercueil Committed by Thomas Bogendoerfer Sep 18, 2020

MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WA



Previously, in cpu_probe_ingenic(), c->writecombine was set to
_CACHE_UNCACHED_ACCELERATED, but this macro was defined differently when
CONFIG_MACH_INGENIC was set. This made it impossible to support multiple
CPUs.

Address this issue by setting c->writecombine to _CACHE_CACHABLE_WA
directly and removing the dependency on CONFIG_MACH_INGENIC.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

parent 7487abbe

arch/mips/include/asm/pgtable-bits.h

+0 −5

Original line number	Diff line number	Diff line
		@@ -249,11 +249,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)

		#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)

		#elif defined(CONFIG_MACH_INGENIC)

		/* Ingenic uses the WA bit to achieve write-combine memory writes */
		#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)

		#endif

		#ifndef _CACHE_CACHABLE_NO_WA

arch/mips/kernel/cpu-probe.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -2169,8 +2169,9 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)

		/* XBurst®1 with MXU2.0 SIMD ISA */
		case PRID_IMP_XBURST_REV2:
		/* Ingenic uses the WA bit to achieve write-combine memory writes */
		c->writecombine = _CACHE_CACHABLE_WA;
		c->cputype = CPU_XBURST;
		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
		__cpu_name[cpu] = "Ingenic XBurst";
		break;