Commit 95aa832b authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/ctrl/aardvark' 

- Add support for AER capability on emulated bridge (Pali Rohár)

- Add support for Slot capability on emulated bridge (Pali Rohár)

* pci/ctrl/aardvark:
  PCI: aardvark: Fix reporting Slot capabilities on emulated bridge
  PCI: aardvark: Add support for AER registers on emulated bridge
parents d22b9e60 bcdb6fd4

drivers/pci/controller/pci-aardvark.c

+103 −9
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>

 */



#include <linux/bitfield.h>

#include <linux/delay.h>

#include <linux/gpio/consumer.h>

#include <linux/interrupt.h>
@@ -33,6 +34,7 @@ 
#define PCIE_CORE_CMD_STATUS_REG				0x4

#define PCIE_CORE_DEV_REV_REG					0x8

#define PCIE_CORE_PCIEXP_CAP					0xc0

#define PCIE_CORE_PCIERR_CAP					0x100

#define PCIE_CORE_ERR_CAPCTL_REG				0x118

#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX			BIT(5)

#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN			BIT(6)
@@ -857,14 +859,11 @@ advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, 




	switch (reg) {

	case PCI_EXP_SLTCTL:

		*value = PCI_EXP_SLTSTA_PDS << 16;

		return PCI_BRIDGE_EMUL_HANDLED;



	/*

	 * PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need

	 * to be handled here, because their values are stored in emulated

	 * config space buffer, and we read them from there when needed.

	 * PCI_EXP_SLTCAP, PCI_EXP_SLTCTL, PCI_EXP_RTCTL and PCI_EXP_RTSTA are

	 * also supported, but do not need to be handled here, because their

	 * values are stored in emulated config space buffer, and we read them

	 * from there when needed.

	 */



	case PCI_EXP_LNKCAP: {
@@ -944,11 +943,89 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, 
	}

}



static pci_bridge_emul_read_status_t

advk_pci_bridge_emul_ext_conf_read(struct pci_bridge_emul *bridge,

				   int reg, u32 *value)

{

	struct advk_pcie *pcie = bridge->data;



	switch (reg) {

	case 0:

		*value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg);



		/*

		 * PCI_EXT_CAP_NEXT bits are set to offset 0x150, but Armada

		 * 3700 Functional Specification does not document registers

		 * at those addresses.

		 *

		 * Thus we clear PCI_EXT_CAP_NEXT bits to make Advanced Error

		 * Reporting Capability header the last Extended Capability.

		 * If we obtain documentation for those registers in the

		 * future, this can be changed.

		 */

		*value &= 0x000fffff;

		return PCI_BRIDGE_EMUL_HANDLED;



	case PCI_ERR_UNCOR_STATUS:

	case PCI_ERR_UNCOR_MASK:

	case PCI_ERR_UNCOR_SEVER:

	case PCI_ERR_COR_STATUS:

	case PCI_ERR_COR_MASK:

	case PCI_ERR_CAP:

	case PCI_ERR_HEADER_LOG + 0:

	case PCI_ERR_HEADER_LOG + 4:

	case PCI_ERR_HEADER_LOG + 8:

	case PCI_ERR_HEADER_LOG + 12:

	case PCI_ERR_ROOT_COMMAND:

	case PCI_ERR_ROOT_STATUS:

	case PCI_ERR_ROOT_ERR_SRC:

		*value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg);

		return PCI_BRIDGE_EMUL_HANDLED;



	default:

		return PCI_BRIDGE_EMUL_NOT_HANDLED;

	}

}



static void

advk_pci_bridge_emul_ext_conf_write(struct pci_bridge_emul *bridge,

				    int reg, u32 old, u32 new, u32 mask)

{

	struct advk_pcie *pcie = bridge->data;



	switch (reg) {

	/* These are W1C registers, so clear other bits */

	case PCI_ERR_UNCOR_STATUS:

	case PCI_ERR_COR_STATUS:

	case PCI_ERR_ROOT_STATUS:

		new &= mask;

		fallthrough;



	case PCI_ERR_UNCOR_MASK:

	case PCI_ERR_UNCOR_SEVER:

	case PCI_ERR_COR_MASK:

	case PCI_ERR_CAP:

	case PCI_ERR_HEADER_LOG + 0:

	case PCI_ERR_HEADER_LOG + 4:

	case PCI_ERR_HEADER_LOG + 8:

	case PCI_ERR_HEADER_LOG + 12:

	case PCI_ERR_ROOT_COMMAND:

	case PCI_ERR_ROOT_ERR_SRC:

		advk_writel(pcie, new, PCIE_CORE_PCIERR_CAP + reg);

		break;



	default:

		break;

	}

}



static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {

	.read_base = advk_pci_bridge_emul_base_conf_read,

	.write_base = advk_pci_bridge_emul_base_conf_write,

	.read_pcie = advk_pci_bridge_emul_pcie_conf_read,

	.write_pcie = advk_pci_bridge_emul_pcie_conf_write,

	.read_ext = advk_pci_bridge_emul_ext_conf_read,

	.write_ext = advk_pci_bridge_emul_ext_conf_write,

};



/*
@@ -977,8 +1054,25 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) 
	/* Support interrupt A for MSI feature */

	bridge->conf.intpin = PCI_INTERRUPT_INTA;



	/* Aardvark HW provides PCIe Capability structure in version 2 */

	bridge->pcie_conf.cap = cpu_to_le16(2);

	/*

	 * Aardvark HW provides PCIe Capability structure in version 2 and

	 * indicate slot support, which is emulated.

	 */

	bridge->pcie_conf.cap = cpu_to_le16(2 | PCI_EXP_FLAGS_SLOT);



	/*

	 * Set Presence Detect State bit permanently since there is no support

	 * for unplugging the card nor detecting whether it is plugged. (If a

	 * platform exists in the future that supports it, via a GPIO for

	 * example, it should be implemented via this bit.)

	 *

	 * Set physical slot number to 1 since there is only one port and zero

	 * value is reserved for ports within the same silicon as Root Port

	 * which is not our case.

	 */

	bridge->pcie_conf.slotcap = cpu_to_le32(FIELD_PREP(PCI_EXP_SLTCAP_PSN,

							   1));

	bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS);



	/* Indicates supports for Completion Retry Status */

	bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS);