Commit 959ed538 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-xilinx-dpsub-20200718' of git://linuxtv.org/pinchartl/media into drm-next 



Xilinx ZynqMP DisplayPort Subsystem driver

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200718001755.GA5962@pendragon.ideasonboard.com
parents 2646699f d76271d2

Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml

0 → 100644
+174 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Xilinx ZynqMP DisplayPort Subsystem



description: |

  The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)

  implements the display and audio pipelines based on the DisplayPort v1.2

  standard. The subsystem includes multiple functional blocks as below:



               +------------------------------------------------------------+

  +--------+   | +----------------+     +-----------+                       |

  | DPDMA  | --->|                | --> |   Video   | Video +-------------+ |

  | 4x vid |   | |                |     | Rendering | -+--> |             | |   +------+

  | 2x aud |   | |  Audio/Video   | --> | Pipeline  |  |    | DisplayPort |---> | PHY0 |

  +--------+   | | Buffer Manager |     +-----------+  |    |   Source    | |   +------+

               | |    and STC     |     +-----------+  |    | Controller  | |   +------+

  Live Video --->|                | --> |   Audio   | Audio |             |---> | PHY1 |

               | |                |     |   Mixer   | --+-> |             | |   +------+

  Live Audio --->|                | --> |           |  ||   +-------------+ |

               | +----------------+     +-----------+  ||                   |

               +---------------------------------------||-------------------+

                                                       vv

                                                 Blended Video and

                                                 Mixed Audio to PL



  The Buffer Manager interacts with external interface such as DMA engines or

  live audio/video streams from the programmable logic. The Video Rendering

  Pipeline blends the video and graphics layers and performs colorspace

  conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort

  Source Controller handles the DisplayPort protocol and connects to external

  PHYs.



  The subsystem supports 2 video and 2 audio streams, and various pixel formats

  and depths up to 4K@30 resolution.



  Please refer to "Zynq UltraScale+ Device Technical Reference Manual"

  (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)

  for more details.



maintainers:

  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>



properties:

  compatible:

    const: xlnx,zynqmp-dpsub-1.7



  reg:

    maxItems: 4

  reg-names:

    items:

      - const: dp

      - const: blend

      - const: av_buf

      - const: aud



  interrupts:

    maxItems: 1



  clocks:

    description:

      The APB clock and at least one video clock are mandatory, the audio clock

      is optional.

    minItems: 2

    maxItems: 4

    items:

      - description: dp_apb_clk is the APB clock

      - description: dp_aud_clk is the Audio clock

      - description:

          dp_vtc_pixel_clk_in is the non-live video clock (from Processing

          System)

      - description:

          dp_live_video_in_clk is the live video clock (from Programmable

          Logic)

  clock-names:

    oneOf:

      - minItems: 2

        maxItems: 3

        items:

          - const: dp_apb_clk

          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]

          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]

      - minItems: 3

        maxItems: 4

        items:

          - const: dp_apb_clk

          - const: dp_aud_clk

          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]

          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]



  power-domains:

    maxItems: 1



  resets:

    maxItems: 1



  dmas:

    maxItems: 4

    items:

      - description: Video layer, plane 0 (RGB or luma)

      - description: Video layer, plane 1 (U/V or U)

      - description: Video layer, plane 2 (V)

      - description: Graphics layer

  dma-names:

    items:

      - const: vid0

      - const: vid1

      - const: vid2

      - const: gfx0



  phys:

    description: PHYs for the DP data lanes

    minItems: 1

    maxItems: 2

  phy-names:

    minItems: 1

    maxItems: 2

    items:

      - const: dp-phy0

      - const: dp-phy1



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - clocks

  - clock-names

  - power-domains

  - resets

  - dmas

  - dma-names

  - phys

  - phy-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/phy/phy.h>

    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>



    display@fd4a0000 {

        compatible = "xlnx,zynqmp-dpsub-1.7";

        reg = <0x0 0xfd4a0000 0x0 0x1000>,

              <0x0 0xfd4aa000 0x0 0x1000>,

              <0x0 0xfd4ab000 0x0 0x1000>,

              <0x0 0xfd4ac000 0x0 0x1000>;

        reg-names = "dp", "blend", "av_buf", "aud";

        interrupts = <0 119 4>;

        interrupt-parent = <&gic>;



        clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";

        clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;



        power-domains = <&pd_dp>;

        resets = <&reset ZYNQMP_RESET_DP>;



        dma-names = "vid0", "vid1", "vid2", "gfx0";

        dmas = <&xlnx_dpdma 0>,

               <&xlnx_dpdma 1>,

               <&xlnx_dpdma 2>,

               <&xlnx_dpdma 3>;



        phys = <&psgtr 1 PHY_TYPE_DP 0 3 27000000>,

               <&psgtr 0 PHY_TYPE_DP 1 3 27000000>;



        phy-names = "dp-phy0", "dp-phy1";

    };



...

Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml

0 → 100644
+68 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings



description: |

  These bindings describe the DMA engine included in the Xilinx ZynqMP

  DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3

  channels for a video stream, 1 channel for a graphics stream, and 2 channels

  for an audio stream).



maintainers:

  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>



allOf:

  - $ref: "../dma-controller.yaml#"



properties:

  "#dma-cells":

    const: 1

    description: |

      The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h

      for a list of channel IDs).



  compatible:

    const: xlnx,zynqmp-dpdma



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    description: The AXI clock

    maxItems: 1



  clock-names:

    const: axi_clk



required:

  - "#dma-cells"

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    dma: dma-controller@fd4c0000 {

      compatible = "xlnx,zynqmp-dpdma";

      reg = <0x0 0xfd4c0000 0x0 0x1000>;

      interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;

      interrupt-parent = <&gic>;

      clocks = <&dpdma_clk>;

      clock-names = "axi_clk";

      #dma-cells = <1>;

    };



...

Documentation/driver-api/dmaengine/client.rst

+3 −1
Original line number Diff line number Diff line
@@ -86,7 +86,9 @@ The details of these operations are: 
  - interleaved_dma: This is common to Slave as well as M2M clients. For slave

    address of devices' fifo could be already known to the driver.

    Various types of operations could be expressed by setting

    appropriate values to the 'dma_interleaved_template' members.

    appropriate values to the 'dma_interleaved_template' members. Cyclic

    interleaved DMA transfers are also possible if supported by the channel by

    setting the DMA_PREP_REPEAT transfer flag.



  A non-NULL return of this transfer API represents a "descriptor" for

  the given transaction.

Documentation/driver-api/dmaengine/provider.rst

+49 −0
Original line number Diff line number Diff line
@@ -239,6 +239,27 @@ Currently, the types available are: 
    want to transfer a portion of uncompressed data directly to the

    display to print it



- DMA_REPEAT



  - The device supports repeated transfers. A repeated transfer, indicated by

    the DMA_PREP_REPEAT transfer flag, is similar to a cyclic transfer in that

    it gets automatically repeated when it ends, but can additionally be

    replaced by the client.



  - This feature is limited to interleaved transfers, this flag should thus not

    be set if the DMA_INTERLEAVE flag isn't set. This limitation is based on

    the current needs of DMA clients, support for additional transfer types

    should be added in the future if and when the need arises.



- DMA_LOAD_EOT



  - The device supports replacing repeated transfers at end of transfer (EOT)

    by queuing a new transfer with the DMA_PREP_LOAD_EOT flag set.



  - Support for replacing a currently running transfer at another point (such

    as end of burst instead of end of transfer) will be added in the future

    based on DMA clients needs, if and when the need arises.



These various types will also affect how the source and destination

addresses change over time.
@@ -531,6 +552,34 @@ DMA_CTRL_REUSE 
    writes for which the descriptor should be in different format from

    normal data descriptors.



- DMA_PREP_REPEAT



  - If set, the transfer will be automatically repeated when it ends until a

    new transfer is queued on the same channel with the DMA_PREP_LOAD_EOT flag.

    If the next transfer to be queued on the channel does not have the

    DMA_PREP_LOAD_EOT flag set, the current transfer will be repeated until the

    client terminates all transfers.



  - This flag is only supported if the channel reports the DMA_REPEAT

    capability.



- DMA_PREP_LOAD_EOT



  - If set, the transfer will replace the transfer currently being executed at

    the end of the transfer.



  - This is the default behaviour for non-repeated transfers, specifying

    DMA_PREP_LOAD_EOT for non-repeated transfers will thus make no difference.



  - When using repeated transfers, DMA clients will usually need to set the

    DMA_PREP_LOAD_EOT flag on all transfers, otherwise the channel will keep

    repeating the last repeated transfer and ignore the new transfers being

    queued. Failure to set DMA_PREP_LOAD_EOT will appear as if the channel was

    stuck on the previous transfer.



  - This flag is only supported if the channel reports the DMA_LOAD_EOT

    capability.



General Design Notes

====================

MAINTAINERS

+18 −0
Original line number Diff line number Diff line
@@ -5839,6 +5839,15 @@ T: git git://anongit.freedesktop.org/drm/drm-misc 
F:	Documentation/gpu/xen-front.rst

F:	drivers/gpu/drm/xen/









DRM DRIVERS FOR XILINX









M:	Hyun Kwon <hyun.kwon@xilinx.com>









M:	Laurent Pinchart <laurent.pinchart@ideasonboard.com>









L:	dri-devel@lists.freedesktop.org









S:	Maintained









T:	git git://anongit.freedesktop.org/drm/drm-misc









F:	Documentation/devicetree/bindings/display/xlnx/









F:	drivers/gpu/drm/xlnx/

















DRM DRIVERS FOR ZTE ZX









M:	Shawn Guo <shawnguo@kernel.org>









L:	dri-devel@lists.freedesktop.org








@@ -18853,6 +18862,15 @@ F:	Documentation/devicetree/bindings/media/xilinx/







F:	drivers/media/platform/xilinx/









F:	include/uapi/linux/xilinx-v4l2-controls.h

















XILINX ZYNQMP DPDMA DRIVER









M:	Hyun Kwon <hyun.kwon@xilinx.com>









M:	Laurent Pinchart <laurent.pinchart@ideasonboard.com>









L:	dmaengine@vger.kernel.org









S:	Supported









F:	Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml









F:	drivers/dma/xilinx/xilinx_dpdma.c









F:	include/dt-bindings/dma/xlnx-zynqmp-dpdma.h

















XILLYBUS DRIVER









M:	Eli Billauer <eli.billauer@gmail.com>









L:	linux-kernel@vger.kernel.org