Commit 95848099 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'stmmac-25gbps' 



Michael Sit Wei Hong says:

====================
Enable 2.5Gbps speed for stmmac

Intel mGbE supports 2.5Gbps link speed by overclocking the clock rate
by 2.5 times to support 2.5Gbps link speed. In this mode, the serdes/PHY
operates at a serial baud rate of 3.125 Gbps and the PCS data path and
GMII interface of the MAC operate at 312.5 MHz instead of 125 MHz.
This is configured in the BIOS during boot up. The kernel driver is not able
access to modify the clock rate for 1Gbps/2.5G mode on the fly. The way to
determine the current 1G/2.5G mode is by reading a dedicated adhoc
register through mdio bus.

Changes:
v5 -> v6
 patch 1/3
 - Check if mdio_bus_data is populated to prevent NULL pointer dereferencing
   when accesing mdio_bus_data member

v4 -> v5
 patch 1/3
 - Rebase to latest code changes after Vladimir's code is merged and fix
   build warnings

v3 -> v4
 patch 1/3
 - Rebase to latest code and Initialize 'found' to 0 to avoid build warning

 patch 2/3
 - Fix indentation issue from v3

v2 -> v3
 patch 1/3
 -New patch added to restructure the code. enabling reading the dedicated
  adhoc register to determine link speed mode.

 patch 2/3
 -Restructure for 2.5G speed to use 2500BaseX configuration as the
  PHY interface.

 patch 3/3
 -Restructure to read serdes registers to set max_speed and configure to
  use 2500BaseX in 2.5G speeds.

v1 -> v2
 patch 1/2
 -Remove MAC supported link speed masking

 patch 2/2
 -Add supported link speed masking in the PCS

iperf3 and ping for 2.5Gbps and regression test on 10M/100M/1000Mbps
is done to prevent regresson issues.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 303597e4 46682cb8

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c

+47 −1
Original line number Diff line number Diff line
@@ -102,6 +102,22 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) 


	serdes_phy_addr = intel_priv->mdio_adhoc_addr;



	/* Set the serdes rate and the PCLK rate */

	data = mdiobus_read(priv->mii, serdes_phy_addr,

			    SERDES_GCR0);



	data &= ~SERDES_RATE_MASK;

	data &= ~SERDES_PCLK_MASK;



	if (priv->plat->max_speed == 2500)

		data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |

			SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;

	else

		data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |

			SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;



	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);



	/* assert clk_req */

	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);

	data |= SERDES_PLL_CLK;
@@ -230,6 +246,32 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) 
	}

}



static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)

{

	struct intel_priv_data *intel_priv = intel_data;

	struct stmmac_priv *priv = netdev_priv(ndev);

	int serdes_phy_addr = 0;

	u32 data = 0;



	serdes_phy_addr = intel_priv->mdio_adhoc_addr;



	/* Determine the link speed mode: 2.5Gbps/1Gbps */

	data = mdiobus_read(priv->mii, serdes_phy_addr,

			    SERDES_GCR);



	if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) ==

	    SERDES_LINK_MODE_2G5) {

		dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");

		priv->plat->max_speed = 2500;

		priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;

		priv->plat->mdio_bus_data->xpcs_an_inband = false;

	} else {

		priv->plat->max_speed = 1000;

		priv->plat->phy_interface = PHY_INTERFACE_MODE_SGMII;

		priv->plat->mdio_bus_data->xpcs_an_inband = true;

	}

}



/* Program PTP Clock Frequency for different variant of

 * Intel mGBE that has slightly different GPO mapping

 */
@@ -586,7 +628,7 @@ static int ehl_sgmii_data(struct pci_dev *pdev, 
{

	plat->bus_id = 1;

	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;



	plat->speed_mode_2500 = intel_speed_mode_2500;

	plat->serdes_powerup = intel_serdes_powerup;

	plat->serdes_powerdown = intel_serdes_powerdown;
@@ -639,6 +681,7 @@ static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, 
				 struct plat_stmmacenet_data *plat)

{

	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;

	plat->speed_mode_2500 = intel_speed_mode_2500;

	plat->serdes_powerup = intel_serdes_powerup;

	plat->serdes_powerdown = intel_serdes_powerdown;

	return ehl_pse0_common_data(pdev, plat);
@@ -677,6 +720,7 @@ static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, 
				 struct plat_stmmacenet_data *plat)

{

	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;

	plat->speed_mode_2500 = intel_speed_mode_2500;

	plat->serdes_powerup = intel_serdes_powerup;

	plat->serdes_powerdown = intel_serdes_powerdown;

	return ehl_pse1_common_data(pdev, plat);
@@ -711,6 +755,7 @@ static int tgl_sgmii_phy0_data(struct pci_dev *pdev, 
{

	plat->bus_id = 1;

	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;

	plat->speed_mode_2500 = intel_speed_mode_2500;

	plat->serdes_powerup = intel_serdes_powerup;

	plat->serdes_powerdown = intel_serdes_powerdown;

	return tgl_common_data(pdev, plat);
@@ -725,6 +770,7 @@ static int tgl_sgmii_phy1_data(struct pci_dev *pdev, 
{

	plat->bus_id = 2;

	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;

	plat->speed_mode_2500 = intel_speed_mode_2500;

	plat->serdes_powerup = intel_serdes_powerup;

	plat->serdes_powerdown = intel_serdes_powerdown;

	return tgl_common_data(pdev, plat);

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h

+13 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#define POLL_DELAY_US 8



/* SERDES Register */

#define SERDES_GCR	0x0	/* Global Conguration */

#define SERDES_GSR0	0x5	/* Global Status Reg0 */

#define SERDES_GCR0	0xb	/* Global Configuration Reg0 */
@@ -17,8 +18,20 @@ 
#define SERDES_PHY_RX_CLK	BIT(1)		/* PSE SGMII PHY rx clk */

#define SERDES_RST		BIT(2)		/* Serdes Reset */

#define SERDES_PWR_ST_MASK	GENMASK(6, 4)	/* Serdes Power state*/

#define SERDES_RATE_MASK	GENMASK(9, 8)

#define SERDES_PCLK_MASK	GENMASK(14, 12)	/* PCLK rate to PHY */

#define SERDES_LINK_MODE_MASK	GENMASK(2, 1)

#define SERDES_LINK_MODE_SHIFT	1

#define SERDES_PWR_ST_SHIFT	4

#define SERDES_PWR_ST_P0	0x0

#define SERDES_PWR_ST_P3	0x3

#define SERDES_LINK_MODE_2G5	0x3

#define SERSED_LINK_MODE_1G	0x2

#define SERDES_PCLK_37p5MHZ	0x0

#define SERDES_PCLK_70MHZ	0x1

#define SERDES_RATE_PCIE_GEN1	0x0

#define SERDES_RATE_PCIE_GEN2	0x1

#define SERDES_RATE_PCIE_SHIFT	8

#define SERDES_PCLK_SHIFT	12



#endif /* __DWMAC_INTEL_H__ */

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

+1 −0
Original line number Diff line number Diff line
@@ -1358,6 +1358,7 @@ int dwmac4_setup(struct stmmac_priv *priv) 
	mac->link.speed10 = GMAC_CONFIG_PS;

	mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;

	mac->link.speed1000 = 0;

	mac->link.speed2500 = GMAC_CONFIG_FES;

	mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;

	mac->mii.addr = GMAC_MDIO_ADDR;

	mac->mii.data = GMAC_MDIO_DATA;

drivers/net/ethernet/stmicro/stmmac/stmmac.h

+1 −0
Original line number Diff line number Diff line
@@ -311,6 +311,7 @@ enum stmmac_state { 
int stmmac_mdio_unregister(struct net_device *ndev);

int stmmac_mdio_register(struct net_device *ndev);

int stmmac_mdio_reset(struct mii_bus *mii);

int stmmac_xpcs_setup(struct mii_bus *mii);

void stmmac_set_ethtool_ops(struct net_device *netdev);



void stmmac_ptp_register(struct stmmac_priv *priv);

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

+16 −0
Original line number Diff line number Diff line
@@ -931,6 +931,10 @@ static void stmmac_validate(struct phylink_config *config, 
	if ((max_speed > 0) && (max_speed < 1000)) {

		phylink_set(mask, 1000baseT_Full);

		phylink_set(mask, 1000baseX_Full);

	} else if (priv->plat->has_gmac4) {

		if (!max_speed || max_speed >= 2500)

			phylink_set(mac_supported, 2500baseT_Full);

			phylink_set(mac_supported, 2500baseX_Full);

	} else if (priv->plat->has_xgmac) {

		if (!max_speed || (max_speed >= 2500)) {

			phylink_set(mac_supported, 2500baseT_Full);
@@ -6993,6 +6997,17 @@ int stmmac_dvr_probe(struct device *device, 
		}

	}



	if (priv->plat->speed_mode_2500)

		priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);



	if (priv->plat->mdio_bus_data) {

		if (priv->plat->mdio_bus_data->has_xpcs) {

			ret = stmmac_xpcs_setup(priv->mii);

			if (ret)

				goto error_xpcs_setup;

		}

	}



	ret = stmmac_phy_setup(priv);

	if (ret) {

		netdev_err(ndev, "failed to setup phy (%d)\n", ret);
@@ -7029,6 +7044,7 @@ int stmmac_dvr_probe(struct device *device, 
	unregister_netdev(ndev);

error_netdev_register:

	phylink_destroy(priv->phylink);

error_xpcs_setup:

error_phy_setup:

	if (priv->hw->pcs != STMMAC_PCS_TBI &&

	    priv->hw->pcs != STMMAC_PCS_RTBI)