Commit 95589cec authored by Swati Sharma's avatar Swati Sharma Committed by Uma Shankar
Browse files

drm/i915/dsc: convert dsc debugfs entry from output_bpp to input_bpc 



Convert dsc debugfs entry from output_bpp to input_bpc. The rationale
is to validate different input bpc across various platforms.

v2: -improved commit message (Jani N)
    -styling fixes (Jani N)

Signed-off-by: default avatarSwati Sharma <swati2.sharma@intel.com>
Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220902190658.9459-2-swati2.sharma@intel.com
parent c73cdd12

drivers/gpu/drm/i915/display/intel_display_debugfs.c

+13 −14
Original line number Diff line number Diff line
@@ -2089,7 +2089,7 @@ static const struct file_operations i915_dsc_fec_support_fops = { 
	.write = i915_dsc_fec_support_write

};



static int i915_dsc_bpp_show(struct seq_file *m, void *data)

static int i915_dsc_bpc_show(struct seq_file *m, void *data)

{

	struct drm_connector *connector = m->private;

	struct drm_device *dev = connector->dev;
@@ -2112,14 +2112,14 @@ static int i915_dsc_bpp_show(struct seq_file *m, void *data) 
	}



	crtc_state = to_intel_crtc_state(crtc->state);

	seq_printf(m, "Compressed_BPP: %d\n", crtc_state->dsc.compressed_bpp);

	seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);



out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);



	return ret;

}



static ssize_t i915_dsc_bpp_write(struct file *file,

static ssize_t i915_dsc_bpc_write(struct file *file,

				  const char __user *ubuf,

				  size_t len, loff_t *offp)

{
@@ -2127,33 +2127,32 @@ static ssize_t i915_dsc_bpp_write(struct file *file, 
		((struct seq_file *)file->private_data)->private;

	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	int dsc_bpp = 0;

	int dsc_bpc = 0;

	int ret;



	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_bpp);

	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_bpc);

	if (ret < 0)

		return ret;



	intel_dp->force_dsc_bpp = dsc_bpp;

	intel_dp->force_dsc_bpc = dsc_bpc;

	*offp += len;



	return len;

}



static int i915_dsc_bpp_open(struct inode *inode,

static int i915_dsc_bpc_open(struct inode *inode,

			     struct file *file)

{

	return single_open(file, i915_dsc_bpp_show,

			   inode->i_private);

	return single_open(file, i915_dsc_bpc_show, inode->i_private);

}



static const struct file_operations i915_dsc_bpp_fops = {

static const struct file_operations i915_dsc_bpc_fops = {

	.owner = THIS_MODULE,

	.open = i915_dsc_bpp_open,

	.open = i915_dsc_bpc_open,

	.read = seq_read,

	.llseek = seq_lseek,

	.release = single_release,

	.write = i915_dsc_bpp_write

	.write = i915_dsc_bpc_write

};



/*
@@ -2223,8 +2222,8 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector) 
		debugfs_create_file("i915_dsc_fec_support", 0644, root,

				    connector, &i915_dsc_fec_support_fops);



		debugfs_create_file("i915_dsc_bpp", 0644, root,

				    connector, &i915_dsc_bpp_fops);

		debugfs_create_file("i915_dsc_bpc", 0644, root,

				    connector, &i915_dsc_bpc_fops);

	}



	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||

drivers/gpu/drm/i915/display/intel_display_types.h

+1 −1
Original line number Diff line number Diff line
@@ -1713,7 +1713,7 @@ struct intel_dp { 


	/* Display stream compression testing */

	bool force_dsc_en;

	int force_dsc_bpp;

	int force_dsc_bpc;



	bool hobl_failed;

	bool hobl_active;

drivers/gpu/drm/i915/display/intel_dp.c

+5 −16
Original line number Diff line number Diff line
@@ -1484,6 +1484,11 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 


	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);



	if (intel_dp->force_dsc_bpc) {

		pipe_bpp = intel_dp->force_dsc_bpc * 3;

		drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);

	}



	/* Min Input BPC for ICL+ is 8 */

	if (pipe_bpp < 8 * 3) {

		drm_dbg_kms(&dev_priv->drm,
@@ -1535,22 +1540,6 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 
		pipe_config->dsc.slice_count = dsc_dp_slice_count;

	}



	/* As of today we support DSC for only RGB */

	if (intel_dp->force_dsc_bpp) {

		if (intel_dp->force_dsc_bpp >= 8 &&

		    intel_dp->force_dsc_bpp < pipe_bpp) {

			drm_dbg_kms(&dev_priv->drm,

				    "DSC BPP forced to %d",

				    intel_dp->force_dsc_bpp);

			pipe_config->dsc.compressed_bpp =

						intel_dp->force_dsc_bpp;

		} else {

			drm_dbg_kms(&dev_priv->drm,

				    "Invalid DSC BPP %d",

				    intel_dp->force_dsc_bpp);

		}

	}



	/*

	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate

	 * is greater than the maximum Cdclock and if slice count is even