Unverified Commit 9534dcd9 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!9883 AMD QoS new features BMEC and SMBA 

Merge Pull Request from: @kile2009 
 
support new features:
Bandwidth Monitoring Event Configuration (BMEC)
Slow Memory Bandwidth allocation (SMBA)

testing:

cat /sys/fs/resctrl/info/L3_MON/mon_features
llc_occupancy
mbm_total_bytes
mbm_total_bytes_config
mbm_local_bytes
mbm_local_bytes_config

sudo bash -c "echo  0=0x33 > /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config"
wwk@localhost:~$ cat  /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config
0=0x33;1=0x7f;2=0x7f;3=0x7f;4=0x7f;5=0x7f;6=0x7f;7=0x7f;8=0x7f;9=0x7f;10=0x7f;11=0x7f


cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config
0=0x15;1=0x15;2=0x15;3=0x15;4=0x15;5=0x15;6=0x15;7=0x15;8=0x15;9=0x15;10=0x15;11=0x15

cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config
0=0x33;1=0x7f;2=0x7f;3=0x7f;4=0x7f;5=0x7f;6=0x7f;7=0x7f;8=0x7f;9=0x7f;10=0x7f;11=0x7f 
 
Link:https://gitee.com/openeuler/kernel/pulls/9883

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Reviewed-by: default avatarZucheng Zheng <zhengzucheng@huawei.com>
Reviewed-by: default avatarLi Nan <linan122@huawei.com>
Signed-off-by: default avatarLi Nan <linan122@huawei.com>
parents 25a1e372 a74904a0

Documentation/admin-guide/kernel-parameters.txt

+1 −1
Original line number Diff line number Diff line
@@ -4845,7 +4845,7 @@ 
	rdt=		[HW,X86,RDT]

			Turn on/off individual RDT features. List is:

			cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp,

			mba.

			mba, smba, bmec.

			E.g. to turn on cmt and turn off mba use:

				rdt=cmt,!mba

arch/x86/include/asm/cpufeatures.h

+2 −0
Original line number Diff line number Diff line
@@ -322,6 +322,8 @@ 
#define X86_FEATURE_RSB_VMEXIT_LITE		(11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */

#define X86_FEATURE_SGX_EDECCSSA	(11*32+18) /* "" SGX EDECCSSA user leaf function */

#define X86_FEATURE_MSR_TSX_CTRL	(11*32+19) /* "" MSR IA32_TSX_CTRL (Intel) implemented */

#define X86_FEATURE_SMBA		(11*32+21) /* "" Slow Memory Bandwidth Allocation */

#define X86_FEATURE_BMEC		(11*32+22) /* "" Bandwidth Monitoring Event Configuration */



#define X86_FEATURE_SRSO		(11*32+24) /* "" AMD BTB untrain RETs */

#define X86_FEATURE_SRSO_ALIAS		(11*32+25) /* "" AMD BTB untrain RETs through aliasing */

arch/x86/include/asm/msr-index.h

+17 −6
Original line number Diff line number Diff line
@@ -4,12 +4,7 @@ 


#include <linux/bits.h>



/*

 * CPU model specific register (MSR) numbers.

 *

 * Do not add new entries to this file unless the definitions are shared

 * between multiple compilation units.

 */

/* CPU model specific register (MSR) numbers. */



/* x86-64 specific MSRs */

#define MSR_EFER		0xc0000080 /* extended feature register */
@@ -1022,6 +1017,22 @@ 
#define VMX_BASIC_MEM_TYPE_WB	6LLU

#define VMX_BASIC_INOUT		0x0040000000000000LLU



/* Resctrl MSRs: */

/* - Intel: */

#define MSR_IA32_L3_QOS_CFG		0xc81

#define MSR_IA32_L2_QOS_CFG		0xc82

#define MSR_IA32_QM_EVTSEL		0xc8d

#define MSR_IA32_QM_CTR			0xc8e

#define MSR_IA32_PQR_ASSOC		0xc8f

#define MSR_IA32_L3_CBM_BASE		0xc90

#define MSR_IA32_L2_CBM_BASE		0xd10

#define MSR_IA32_MBA_THRTL_BASE		0xd50



/* - AMD: */

#define MSR_IA32_MBA_BW_BASE		0xc0000200

#define MSR_IA32_SMBA_BW_BASE		0xc0000280

#define MSR_IA32_EVT_CFG_BASE		0xc0000400



/* MSR_IA32_VMX_MISC bits */

#define MSR_IA32_VMX_MISC_INTEL_PT                 (1ULL << 14)

#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)

arch/x86/include/asm/resctrl.h

+3 −5
Original line number Diff line number Diff line
@@ -7,8 +7,6 @@ 
#include <linux/sched.h>

#include <linux/jump_label.h>



#define IA32_PQR_ASSOC	0x0c8f



/**

 * struct resctrl_pqr_state - State cache for the PQR MSR

 * @cur_rmid:		The cached Resource Monitoring ID
@@ -16,8 +14,8 @@ 
 * @default_rmid:	The user assigned Resource Monitoring ID

 * @default_closid:	The user assigned cached Class Of Service ID

 *

 * The upper 32 bits of IA32_PQR_ASSOC contain closid and the

 * lower 10 bits rmid. The update to IA32_PQR_ASSOC always

 * The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the

 * lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always

 * contains both parts, so we need to cache them. This also

 * stores the user configured per cpu CLOSID and RMID.

 *
@@ -77,7 +75,7 @@ static inline void __resctrl_sched_in(struct task_struct *tsk) 
	if (closid != state->cur_closid || rmid != state->cur_rmid) {

		state->cur_closid = closid;

		state->cur_rmid = rmid;

		wrmsr(IA32_PQR_ASSOC, rmid, closid);

		wrmsr(MSR_IA32_PQR_ASSOC, rmid, closid);

	}

}

arch/x86/kernel/cpu/cpuid-deps.c

+2 −0
Original line number Diff line number Diff line
@@ -68,6 +68,8 @@ static const struct cpuid_dep cpuid_deps[] = { 
	{ X86_FEATURE_CQM_OCCUP_LLC,		X86_FEATURE_CQM_LLC   },

	{ X86_FEATURE_CQM_MBM_TOTAL,		X86_FEATURE_CQM_LLC   },

	{ X86_FEATURE_CQM_MBM_LOCAL,		X86_FEATURE_CQM_LLC   },

	{ X86_FEATURE_BMEC,			X86_FEATURE_CQM_MBM_TOTAL   },

	{ X86_FEATURE_BMEC,			X86_FEATURE_CQM_MBM_LOCAL   },

	{ X86_FEATURE_AVX512_BF16,		X86_FEATURE_AVX512VL  },

	{ X86_FEATURE_AVX512_FP16,		X86_FEATURE_AVX512BW  },

	{ X86_FEATURE_ENQCMD,			X86_FEATURE_XSAVES    },