Unverified Commit 94d50bef authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!15660 v2 add support DVMBM in HIP12 

Merge Pull Request from: @ci-robot 
 
PR sync from: Jinqian Yang <yangjinqian1@huawei.com>
https://mailweb.openeuler.org/archives/list/kernel@openeuler.org/message/MJOJVUQ2UTOL5CE57Z6XPSRIULYA2QKN/ 
Patch#1 kvm: hisi_virt: fix kernel panic when enable DVMBM in nVHE
Patch#2 kvm: hisi_virt: Update TLBI broadcast feature for hip12
Patch#3 KVM: arm64: Add new HiSi CPU type to support DVMBM

Xiang Chen (1):
  kvm: hisi_virt: Update TLBI broadcast feature for hip12

yangjinqian (2):
  kvm: hisi_virt: fix kernel panic when enable DVMBM in nVHE
  KVM: arm64: Add new HiSi CPU type to support DVMBM

 
https://gitee.com/openeuler/kernel/issues/IBTXY2 
 
Link:https://gitee.com/openeuler/kernel/pulls/15660

 

Reviewed-by: default avatarKevin Zhu <zhukeqian1@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents b28aab59 0c2bca09

arch/arm64/kvm/hisilicon/hisi_virt.c

+68 −4
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ static const char * const hisi_cpu_type_str[] = { 
	"HIP09",

	"HIP10",

	"HIP10C",

	"HIP12",

	"Unknown"

};
@@ -30,7 +31,8 @@ static const char * const oem_str[] = { 
	"HIP08   ",	/* Hisi 1620 */

	"HIP09   ",	/* HIP09 */

	"HIP10   ",	/* HIP10 */

	"HIP10C  "	/* HIP10C */

	"HIP10C  ",	/* HIP10C */

	"HIP12   "	/* HIP12 */

};



/*
@@ -157,15 +159,21 @@ static void hardware_disable_dvmbm(void *data) 


bool hisi_dvmbm_supported(void)

{

	if (cpu_type != HI_IP10 && cpu_type != HI_IP10C)

	if (cpu_type != HI_IP10 && cpu_type != HI_IP10C &&

	    cpu_type != HI_IP12)

		return false;



	if (!is_kernel_in_hyp_mode()) {

		kvm_info("Hisi dvmbm not supported by KVM nVHE mode\n");

		return false;

	}



	/* Determine whether DVMBM is supported by the hardware */

	if (!(read_sysreg(aidr_el1) & AIDR_EL1_DVMBM_MASK))

		return false;



	/* User provided kernel command-line parameter */

	if (!dvmbm_enabled || !is_kernel_in_hyp_mode()) {

	if (!dvmbm_enabled) {

		on_each_cpu(hardware_disable_dvmbm, NULL, 1);

		return false;

	}
@@ -391,6 +399,56 @@ static void kvm_update_vm_lsudvmbm(struct kvm *kvm) 
	kvm->arch.tlbi_dvmbm = val;

}



static void kvm_update_vm_lsudvmbm_hip12(struct kvm *kvm)

{

	u64 mpidr, aff3, aff2;

	u64 vm_aff3s[DVMBM_MAX_DIES_HIP12];

	u64 val;

	int cpu, nr_dies;



	nr_dies = kvm_dvmbm_get_dies_info(kvm, vm_aff3s, DVMBM_MAX_DIES_HIP12);

	if (nr_dies > 2) {

		val = DVMBM_RANGE_ALL_DIES << DVMBM_RANGE_SHIFT;

		goto out_update;

	}



	if (nr_dies == 1) {

		val = DVMBM_RANGE_ONE_DIE << DVMBM_RANGE_SHIFT	|

		      vm_aff3s[0] << DVMBM_DIE1_VDIE_SHIFT_HIP12;



		/* fulfill bits [11:6] */

		for_each_cpu(cpu, kvm->arch.sched_cpus) {

			mpidr = cpu_logical_map(cpu);

			aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);



			val |= 1ULL << (aff2 + DVMBM_DIE1_CLUSTER_SHIFT_HIP12);

		}



		goto out_update;

	}



	/* nr_dies == 2 */

	val = DVMBM_RANGE_TWO_DIES << DVMBM_RANGE_SHIFT	|

	      DVMBM_GRAN_CLUSTER << DVMBM_GRAN_SHIFT	|

	      vm_aff3s[0] << DVMBM_DIE1_VDIE_SHIFT_HIP12    |

	      vm_aff3s[1] << DVMBM_DIE2_VDIE_SHIFT_HIP12;



	/* and fulfill bits [11:0] */

	for_each_cpu(cpu, kvm->arch.sched_cpus) {

		mpidr = cpu_logical_map(cpu);

		aff3 = MPIDR_AFFINITY_LEVEL(mpidr, 3);

		aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);



		if (aff3 == vm_aff3s[0])

			val |= 1ULL << (aff2 + DVMBM_DIE1_CLUSTER_SHIFT_HIP12);

		else

			val |= 1ULL << (aff2 + DVMBM_DIE2_CLUSTER_SHIFT_HIP12);

	}



out_update:

	kvm->arch.tlbi_dvmbm = val;

}



void kvm_tlbi_dvmbm_vcpu_load(struct kvm_vcpu *vcpu)

{

	struct kvm *kvm = vcpu->kvm;
@@ -435,6 +493,9 @@ void kvm_tlbi_dvmbm_vcpu_load(struct kvm_vcpu *vcpu) 
	 * Re-calculate LSUDVMBM_EL2 for this VM and kick all vcpus

	 * out to reload the LSUDVMBM configuration.

	 */

	if (cpu_type == HI_IP12)

		kvm_update_vm_lsudvmbm_hip12(kvm);

	else

		kvm_update_vm_lsudvmbm(kvm);

	kvm_make_all_cpus_request(kvm, KVM_REQ_RELOAD_TLBI_DVMBM);
@@ -459,6 +520,9 @@ void kvm_get_pg_cfg(void) 
	u64 mn_phy_base;

	u32 val;



	if (cpu_type == HI_IP12)

		return;



	socket_num = kvm_get_socket_num();

	die_num = kvm_get_die_num();

arch/arm64/kvm/hisilicon/hisi_virt.h

+8 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ enum hisi_cpu_type { 
	HI_IP09,

	HI_IP10,

	HI_IP10C,

	HI_IP12,

	UNKNOWN_HI_TYPE

};
@@ -64,6 +65,13 @@ enum hisi_cpu_type { 


#define DVMBM_MAX_DIES			32



/* HIP12 */

#define DVMBM_DIE1_VDIE_SHIFT_HIP12		57

#define DVMBM_DIE2_VDIE_SHIFT_HIP12		53

#define DVMBM_DIE1_CLUSTER_SHIFT_HIP12		6

#define DVMBM_DIE2_CLUSTER_SHIFT_HIP12		0

#define DVMBM_MAX_DIES_HIP12				8



void probe_hisi_cpu_type(void);

bool hisi_ncsnp_supported(void);

bool hisi_dvmbm_supported(void);