Commit 94aca082 authored by Yangbo Lu's avatar Yangbo Lu Committed by David S. Miller
Browse files

net: mscc: ocelot: add wave programming registers definitions 



Add wave programming registers definitions for Ocelot platforms.

Signed-off-by: default avatarYangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3007bc73

drivers/net/dsa/ocelot/felix_vsc9959.c

+2 −0
Original line number Diff line number Diff line
@@ -313,6 +313,8 @@ static const u32 vsc9959_ptp_regmap[] = { 
	REG(PTP_PIN_TOD_SEC_MSB,           0x000004),

	REG(PTP_PIN_TOD_SEC_LSB,           0x000008),

	REG(PTP_PIN_TOD_NSEC,              0x00000c),

	REG(PTP_PIN_WF_HIGH_PERIOD,        0x000014),

	REG(PTP_PIN_WF_LOW_PERIOD,         0x000018),

	REG(PTP_CFG_MISC,                  0x0000a0),

	REG(PTP_CLK_CFG_ADJ_CFG,           0x0000a4),

	REG(PTP_CLK_CFG_ADJ_FREQ,          0x0000a8),

drivers/net/ethernet/mscc/ocelot_regs.c

+2 −0
Original line number Diff line number Diff line
@@ -239,6 +239,8 @@ static const u32 ocelot_ptp_regmap[] = { 
	REG(PTP_PIN_TOD_SEC_MSB,           0x000004),

	REG(PTP_PIN_TOD_SEC_LSB,           0x000008),

	REG(PTP_PIN_TOD_NSEC,              0x00000c),

	REG(PTP_PIN_WF_HIGH_PERIOD,        0x000014),

	REG(PTP_PIN_WF_LOW_PERIOD,         0x000018),

	REG(PTP_CFG_MISC,                  0x0000a0),

	REG(PTP_CLK_CFG_ADJ_CFG,           0x0000a4),

	REG(PTP_CLK_CFG_ADJ_FREQ,          0x0000a8),

include/soc/mscc/ocelot.h

+2 −0
Original line number Diff line number Diff line
@@ -385,6 +385,8 @@ enum ocelot_reg { 
	PTP_PIN_TOD_SEC_MSB,

	PTP_PIN_TOD_SEC_LSB,

	PTP_PIN_TOD_NSEC,

	PTP_PIN_WF_HIGH_PERIOD,

	PTP_PIN_WF_LOW_PERIOD,

	PTP_CFG_MISC,

	PTP_CLK_CFG_ADJ_CFG,

	PTP_CLK_CFG_ADJ_FREQ,

include/soc/mscc/ocelot_ptp.h

+2 −0
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ 
#define PTP_PIN_TOD_SEC_MSB_RSZ		PTP_PIN_CFG_RSZ

#define PTP_PIN_TOD_SEC_LSB_RSZ		PTP_PIN_CFG_RSZ

#define PTP_PIN_TOD_NSEC_RSZ		PTP_PIN_CFG_RSZ

#define PTP_PIN_WF_HIGH_PERIOD_RSZ	PTP_PIN_CFG_RSZ

#define PTP_PIN_WF_LOW_PERIOD_RSZ	PTP_PIN_CFG_RSZ



#define PTP_PIN_CFG_DOM			BIT(0)

#define PTP_PIN_CFG_SYNC		BIT(2)