Unverified Commit 946ee1f8 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!12338 drm/amd/display: Add NULL pointer check for kzalloc 

Merge Pull Request from: @ci-robot 
 
PR sync from: Chen Jun <chenjun102@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/ZNKWNQWGMPBIQKEB5KWZPMVVYT6KGIRX/ 
 
https://gitee.com/src-openeuler/kernel/issues/IAGSKH 
 
Link:https://gitee.com/openeuler/kernel/pulls/12338

 

Reviewed-by: default avatarWeilong Chen <chenweilong@huawei.com>
Reviewed-by: default avatarZhang Peng <zhangpeng362@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents 0d171de1 b04c6217

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

+8 −0
Original line number Diff line number Diff line
@@ -560,11 +560,19 @@ void dcn3_clk_mgr_construct( 
	dce_clock_read_ss_info(clk_mgr);



	clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);

	if (!clk_mgr->base.bw_params) {

		BREAK_TO_DEBUGGER();

		return;

	}



	/* need physical address of table to give to PMFW */

	clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,

			DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),

			&clk_mgr->wm_range_table_addr);

	if (!clk_mgr->wm_range_table) {

		BREAK_TO_DEBUGGER();

		return;

	}

}



void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+8 −0
Original line number Diff line number Diff line
@@ -1022,11 +1022,19 @@ void dcn32_clk_mgr_construct( 
	clk_mgr->smu_present = false;



	clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);

	if (!clk_mgr->base.bw_params) {

		BREAK_TO_DEBUGGER();

		return;

	}



	/* need physical address of table to give to PMFW */

	clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,

			DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),

			&clk_mgr->wm_range_table_addr);

	if (!clk_mgr->wm_range_table) {

		BREAK_TO_DEBUGGER();

		return;

	}

}



void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

+3 −0
Original line number Diff line number Diff line
@@ -2045,6 +2045,9 @@ bool dcn30_validate_bandwidth(struct dc *dc, 


	BW_VAL_TRACE_COUNT();



	if (!pipes)

		goto validate_fail;



	DC_FP_START();

	out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);

	DC_FP_END();

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

+5 −0
Original line number Diff line number Diff line
@@ -1308,6 +1308,8 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 


	/* allocate HPO link encoder */

	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);

	if (!hpo_dp_enc31)

		return NULL; /* out of memory */



	hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,

					&hpo_dp_link_enc_regs[inst],
@@ -1764,6 +1766,9 @@ bool dcn31_validate_bandwidth(struct dc *dc, 


	BW_VAL_TRACE_COUNT();



	if (!pipes)

		goto validate_fail;



	DC_FP_START();

	out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);

	DC_FP_END();

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c

+5 −0
Original line number Diff line number Diff line
@@ -1381,6 +1381,8 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 


	/* allocate HPO link encoder */

	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);

	if (!hpo_dp_enc31)

		return NULL; /* out of memory */



	hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,

					&hpo_dp_link_enc_regs[inst],
@@ -1741,6 +1743,9 @@ bool dcn314_validate_bandwidth(struct dc *dc, 


	BW_VAL_TRACE_COUNT();



	if (!pipes)

		goto validate_fail;



	if (filter_modes_for_single_channel_workaround(dc, context))

		goto validate_fail;