Loading arch/arm/include/asm/memory.h +4 −3 Original line number Diff line number Diff line Loading @@ -160,10 +160,11 @@ extern unsigned long vectors_base; /* * Physical start and end address of the kernel sections. These addresses are * 2MB-aligned to match the section mappings placed over the kernel. * 2MB-aligned to match the section mappings placed over the kernel. We use * u64 so that LPAE mappings beyond the 32bit limit will work out as well. */ extern u32 kernel_sec_start; extern u32 kernel_sec_end; extern u64 kernel_sec_start; extern u64 kernel_sec_end; /* * Physical vs virtual RAM address space conversion. These are Loading arch/arm/kernel/head.S +14 −3 Original line number Diff line number Diff line Loading @@ -49,7 +49,8 @@ /* * This needs to be assigned at runtime when the linker symbols are * resolved. * resolved. These are unsigned 64bit really, but in this assembly code * We store them as 32bit. */ .pushsection .data .align 2 Loading @@ -57,7 +58,9 @@ .globl kernel_sec_end kernel_sec_start: .long 0 .long 0 kernel_sec_end: .long 0 .long 0 .popsection Loading Loading @@ -250,7 +253,11 @@ __create_page_tables: add r0, r4, #KERNEL_OFFSET >> (SECTION_SHIFT - PMD_ORDER) ldr r6, =(_end - 1) adr_l r5, kernel_sec_start @ _pa(kernel_sec_start) str r8, [r5] @ Save physical start of kernel #ifdef CONFIG_CPU_ENDIAN_BE8 str r8, [r5, #4] @ Save physical start of kernel (BE) #else str r8, [r5] @ Save physical start of kernel (LE) #endif orr r3, r8, r7 @ Add the MMU flags add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 1: str r3, [r0], #1 << PMD_ORDER Loading @@ -259,7 +266,11 @@ __create_page_tables: bls 1b eor r3, r3, r7 @ Remove the MMU flags adr_l r5, kernel_sec_end @ _pa(kernel_sec_end) str r3, [r5] @ Save physical end of kernel #ifdef CONFIG_CPU_ENDIAN_BE8 str r3, [r5, #4] @ Save physical end of kernel (BE) #else str r3, [r5] @ Save physical end of kernel (LE) #endif #ifdef CONFIG_XIP_KERNEL /* Loading arch/arm/mm/mmu.c +8 −1 Original line number Diff line number Diff line Loading @@ -1608,6 +1608,13 @@ static void __init early_paging_init(const struct machine_desc *mdesc) if (offset == 0) return; /* * Offset the kernel section physical offsets so that the kernel * mapping will work out later on. */ kernel_sec_start += offset; kernel_sec_end += offset; /* * Get the address of the remap function in the 1:1 identity * mapping setup by the early page table assembly code. We Loading Loading @@ -1716,7 +1723,7 @@ void __init paging_init(const struct machine_desc *mdesc) { void *zero_page; pr_debug("physical kernel sections: 0x%08x-0x%08x\n", pr_debug("physical kernel sections: 0x%08llx-0x%08llx\n", kernel_sec_start, kernel_sec_end); prepare_page_table(); Loading arch/arm/mm/pv-fixup-asm.S +1 −1 Original line number Diff line number Diff line Loading @@ -29,7 +29,7 @@ ENTRY(lpae_pgtables_remap_asm) ldr r6, =(_end - 1) add r7, r2, #0x1000 add r6, r7, r6, lsr #SECTION_SHIFT - L2_ORDER add r7, r7, #PAGE_OFFSET >> (SECTION_SHIFT - L2_ORDER) add r7, r7, #KERNEL_OFFSET >> (SECTION_SHIFT - L2_ORDER) 1: ldrd r4, r5, [r7] adds r4, r4, r0 adc r5, r5, r1 Loading Loading
arch/arm/include/asm/memory.h +4 −3 Original line number Diff line number Diff line Loading @@ -160,10 +160,11 @@ extern unsigned long vectors_base; /* * Physical start and end address of the kernel sections. These addresses are * 2MB-aligned to match the section mappings placed over the kernel. * 2MB-aligned to match the section mappings placed over the kernel. We use * u64 so that LPAE mappings beyond the 32bit limit will work out as well. */ extern u32 kernel_sec_start; extern u32 kernel_sec_end; extern u64 kernel_sec_start; extern u64 kernel_sec_end; /* * Physical vs virtual RAM address space conversion. These are Loading
arch/arm/kernel/head.S +14 −3 Original line number Diff line number Diff line Loading @@ -49,7 +49,8 @@ /* * This needs to be assigned at runtime when the linker symbols are * resolved. * resolved. These are unsigned 64bit really, but in this assembly code * We store them as 32bit. */ .pushsection .data .align 2 Loading @@ -57,7 +58,9 @@ .globl kernel_sec_end kernel_sec_start: .long 0 .long 0 kernel_sec_end: .long 0 .long 0 .popsection Loading Loading @@ -250,7 +253,11 @@ __create_page_tables: add r0, r4, #KERNEL_OFFSET >> (SECTION_SHIFT - PMD_ORDER) ldr r6, =(_end - 1) adr_l r5, kernel_sec_start @ _pa(kernel_sec_start) str r8, [r5] @ Save physical start of kernel #ifdef CONFIG_CPU_ENDIAN_BE8 str r8, [r5, #4] @ Save physical start of kernel (BE) #else str r8, [r5] @ Save physical start of kernel (LE) #endif orr r3, r8, r7 @ Add the MMU flags add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 1: str r3, [r0], #1 << PMD_ORDER Loading @@ -259,7 +266,11 @@ __create_page_tables: bls 1b eor r3, r3, r7 @ Remove the MMU flags adr_l r5, kernel_sec_end @ _pa(kernel_sec_end) str r3, [r5] @ Save physical end of kernel #ifdef CONFIG_CPU_ENDIAN_BE8 str r3, [r5, #4] @ Save physical end of kernel (BE) #else str r3, [r5] @ Save physical end of kernel (LE) #endif #ifdef CONFIG_XIP_KERNEL /* Loading
arch/arm/mm/mmu.c +8 −1 Original line number Diff line number Diff line Loading @@ -1608,6 +1608,13 @@ static void __init early_paging_init(const struct machine_desc *mdesc) if (offset == 0) return; /* * Offset the kernel section physical offsets so that the kernel * mapping will work out later on. */ kernel_sec_start += offset; kernel_sec_end += offset; /* * Get the address of the remap function in the 1:1 identity * mapping setup by the early page table assembly code. We Loading Loading @@ -1716,7 +1723,7 @@ void __init paging_init(const struct machine_desc *mdesc) { void *zero_page; pr_debug("physical kernel sections: 0x%08x-0x%08x\n", pr_debug("physical kernel sections: 0x%08llx-0x%08llx\n", kernel_sec_start, kernel_sec_end); prepare_page_table(); Loading
arch/arm/mm/pv-fixup-asm.S +1 −1 Original line number Diff line number Diff line Loading @@ -29,7 +29,7 @@ ENTRY(lpae_pgtables_remap_asm) ldr r6, =(_end - 1) add r7, r2, #0x1000 add r6, r7, r6, lsr #SECTION_SHIFT - L2_ORDER add r7, r7, #PAGE_OFFSET >> (SECTION_SHIFT - L2_ORDER) add r7, r7, #KERNEL_OFFSET >> (SECTION_SHIFT - L2_ORDER) 1: ldrd r4, r5, [r7] adds r4, r4, r0 adc r5, r5, r1 Loading