Commit 944823c9 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/xehp: Define compute class and engine 



Introduce a Compute Command Streamer (CCS), which has access to
the media and GPGPU pipelines (but not the 3D pipeline).

To begin with, define the compute class/engine common functions, based
on the existing render ones.

v2:
 - Add kerneldoc for drm_i915_gem_engine_class since we're adding a new
   element to it.  (Daniel)
 - Make engine class <-> guc class converters use lookup tables to make
   it more clear/explicit how the IDs map.  (Tvrtko)

v3:
 - Don't update uapi for now; we'll just include the driver-internal
   changes for the time being.

Bspec: 46167, 45544
Original-author: Michel Thierry
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarAravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> #v1
Link: https://patchwork.freedesktop.org/patch/msgid/20220301231549.1817978-2-matthew.d.roper@intel.com
parent a8b2b8b0

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+28 −0
Original line number Diff line number Diff line
@@ -156,6 +156,34 @@ static const struct engine_info intel_engines[] = { 
			{ .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }

		},

	},

	[CCS0] = {

		.class = COMPUTE_CLASS,

		.instance = 0,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }

		}

	},

	[CCS1] = {

		.class = COMPUTE_CLASS,

		.instance = 1,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }

		}

	},

	[CCS2] = {

		.class = COMPUTE_CLASS,

		.instance = 2,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }

		}

	},

	[CCS3] = {

		.class = COMPUTE_CLASS,

		.instance = 3,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }

		}

	},

};



/**

drivers/gpu/drm/i915/gt/intel_engine_types.h

+8 −1
Original line number Diff line number Diff line
@@ -33,7 +33,8 @@ 
#define VIDEO_ENHANCEMENT_CLASS	2

#define COPY_ENGINE_CLASS	3

#define OTHER_CLASS		4

#define MAX_ENGINE_CLASS	4

#define COMPUTE_CLASS		5

#define MAX_ENGINE_CLASS	5

#define MAX_ENGINE_INSTANCE	7



#define I915_MAX_SLICES	3
@@ -95,6 +96,7 @@ struct i915_ctx_workarounds { 


#define I915_MAX_VCS	8

#define I915_MAX_VECS	4

#define I915_MAX_CCS	4



/*

 * Engine IDs definitions.
@@ -117,6 +119,11 @@ enum intel_engine_id { 
	VECS2,

	VECS3,

#define _VECS(n) (VECS0 + (n))

	CCS0,

	CCS1,

	CCS2,

	CCS3,

#define _CCS(n) (CCS0 + (n))

	I915_NUM_ENGINES

#define INVALID_ENGINE ((enum intel_engine_id)-1)

};

drivers/gpu/drm/i915/gt/intel_engine_user.c

+4 −1
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ static const u8 uabi_classes[] = { 
	[COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,

	[VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,

	[VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,

	/* TODO: Add COMPUTE_CLASS mapping once ABI is available */

};



static int engine_cmp(void *priv, const struct list_head *A,
@@ -139,6 +140,7 @@ const char *intel_engine_class_repr(u8 class) 
		[COPY_ENGINE_CLASS] = "bcs",

		[VIDEO_DECODE_CLASS] = "vcs",

		[VIDEO_ENHANCEMENT_CLASS] = "vecs",

		[COMPUTE_CLASS] = "ccs",

	};



	if (class >= ARRAY_SIZE(uabi_names) || !uabi_names[class])
@@ -162,6 +164,7 @@ static int legacy_ring_idx(const struct legacy_ring *ring) 
		[COPY_ENGINE_CLASS] = { BCS0, 1 },

		[VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },

		[VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS },

		[COMPUTE_CLASS] = { CCS0, I915_MAX_CCS },

	};



	if (GEM_DEBUG_WARN_ON(ring->class >= ARRAY_SIZE(map)))
@@ -190,7 +193,7 @@ static void add_legacy_ring(struct legacy_ring *ring, 
void intel_engines_driver_register(struct drm_i915_private *i915)

{

	struct legacy_ring ring = {};

	u8 uabi_instances[4] = {};

	u8 uabi_instances[5] = {};

	struct list_head *it, *next;

	struct rb_node **p, *prev;

	LIST_HEAD(engines);

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+4 −0
Original line number Diff line number Diff line
@@ -1452,6 +1452,10 @@ 
#define   GEN11_KCR				(19)

#define   GEN11_GTPM				(16)

#define   GEN11_BCS				(15)

#define   GEN12_CCS3				(7)

#define   GEN12_CCS2				(6)

#define   GEN12_CCS1				(5)

#define   GEN12_CCS0				(4)

#define   GEN11_RCS0				(0)

#define   GEN11_VECS(x)				(31 - (x))

#define   GEN11_VCS(x)				(x)

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

+23 −9
Original line number Diff line number Diff line
@@ -46,8 +46,8 @@ 
#define GUC_VIDEO_CLASS			1

#define GUC_VIDEOENHANCE_CLASS		2

#define GUC_BLITTER_CLASS		3

#define GUC_RESERVED_CLASS		4

#define GUC_LAST_ENGINE_CLASS		GUC_RESERVED_CLASS

#define GUC_COMPUTE_CLASS		4

#define GUC_LAST_ENGINE_CLASS		GUC_COMPUTE_CLASS

#define GUC_MAX_ENGINE_CLASSES		16

#define GUC_MAX_INSTANCES_PER_CLASS	32
@@ -156,23 +156,37 @@ FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \ 
FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, c) \

)



/* the GuC arrays don't include OTHER_CLASS */

static u8 engine_class_guc_class_map[] = {

	[RENDER_CLASS]            = GUC_RENDER_CLASS,

	[COPY_ENGINE_CLASS]       = GUC_BLITTER_CLASS,

	[VIDEO_DECODE_CLASS]      = GUC_VIDEO_CLASS,

	[VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS,

	[COMPUTE_CLASS]           = GUC_COMPUTE_CLASS,

};



static u8 guc_class_engine_class_map[] = {

	[GUC_RENDER_CLASS]       = RENDER_CLASS,

	[GUC_BLITTER_CLASS]      = COPY_ENGINE_CLASS,

	[GUC_VIDEO_CLASS]        = VIDEO_DECODE_CLASS,

	[GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS,

	[GUC_COMPUTE_CLASS]      = COMPUTE_CLASS,

};



static inline u8 engine_class_to_guc_class(u8 class)

{

	BUILD_BUG_ON(GUC_RENDER_CLASS != RENDER_CLASS);

	BUILD_BUG_ON(GUC_BLITTER_CLASS != COPY_ENGINE_CLASS);

	BUILD_BUG_ON(GUC_VIDEO_CLASS != VIDEO_DECODE_CLASS);

	BUILD_BUG_ON(GUC_VIDEOENHANCE_CLASS != VIDEO_ENHANCEMENT_CLASS);

	BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1);

	GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);



	return class;

	return engine_class_guc_class_map[class];

}



static inline u8 guc_class_to_engine_class(u8 guc_class)

{

	BUILD_BUG_ON(ARRAY_SIZE(guc_class_engine_class_map) != GUC_LAST_ENGINE_CLASS + 1);

	GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS);

	GEM_BUG_ON(guc_class == GUC_RESERVED_CLASS);



	return guc_class;

	return guc_class_engine_class_map[guc_class];

}



/* Work item for submitting workloads into work queue of GuC. */