Commit 943682e3 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Introduce Jasper Lake PCH 



The Jasper Lake PCH follows ICP/TGP's south display behavior and is
identical to MCC graphics-wise except that it does not use the unusual
(port C -> TC1) pin mapping that MCC does.

Also, it turns out the extra PCH ID that we had previously thought was a
form of MCC is actually a second ID for JSP (i.e., port C uses the port
C pins instead of the TC1 pins).

v2:
 - Also update the port masks (not just the pin table) in
   mcc_hpd_irq_setup.  (Vivek)

v3:
 - Break jsp_hpd_irq_setup out into its own function for clarity.
   (Vivek)

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Vivek Kasireddy <vivek.kasireddy@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarVivek Kasireddy <vivek.kasireddy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015162854.30546-1-matthew.d.roper@intel.com
parent fcb9bba4

drivers/gpu/drm/i915/i915_irq.c

+23 −1
Original line number Diff line number Diff line
@@ -2248,12 +2248,19 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 
		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;

		tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;

		pins = hpd_tgp;

	} else if (HAS_PCH_JSP(dev_priv)) {

		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;

		tc_hotplug_trigger = 0;

		pins = hpd_tgp;

	} else if (HAS_PCH_MCC(dev_priv)) {

		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;

		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);

		tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;

		pins = hpd_icp;

	} else {

		WARN(!HAS_PCH_ICP(dev_priv),

		     "Unrecognized PCH type 0x%x\n", INTEL_PCH_TYPE(dev_priv));



		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;

		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;

		tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
@@ -3383,6 +3390,19 @@ static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) 
			  hpd_icp);

}



/*

 * JSP behaves exactly the same as MCC above except that port C is mapped to

 * the DDI-C pins instead of the TC1 pins.  This means we should follow TGP's

 * masks & tables rather than ICP's masks & tables.

 */

static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)

{

	icp_hpd_irq_setup(dev_priv,

			  SDE_DDI_MASK_TGP, 0,

			  TGP_DDI_HPD_ENABLE_MASK, 0,

			  hpd_tgp);

}



static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)

{

	u32 hotplug;
@@ -4314,7 +4334,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv) 
		if (I915_HAS_HOTPLUG(dev_priv))

			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;

	} else {

		if (HAS_PCH_MCC(dev_priv))

		if (HAS_PCH_JSP(dev_priv))

			dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;

		else if (HAS_PCH_MCC(dev_priv))

			dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;

		else if (INTEL_GEN(dev_priv) >= 11)

			dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;

drivers/gpu/drm/i915/intel_pch.c

+5 −1
Original line number Diff line number Diff line
@@ -79,7 +79,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) 
		WARN_ON(!IS_ICELAKE(dev_priv));

		return PCH_ICP;

	case INTEL_PCH_MCC_DEVICE_ID_TYPE:

	case INTEL_PCH_MCC2_DEVICE_ID_TYPE:

		DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");

		WARN_ON(!IS_ELKHARTLAKE(dev_priv));

		return PCH_MCC;
@@ -87,6 +86,11 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) 
		DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");

		WARN_ON(!IS_TIGERLAKE(dev_priv));

		return PCH_TGP;

	case INTEL_PCH_JSP_DEVICE_ID_TYPE:

	case INTEL_PCH_JSP2_DEVICE_ID_TYPE:

		DRM_DEBUG_KMS("Found Jasper Lake PCH\n");

		WARN_ON(!IS_ELKHARTLAKE(dev_priv));

		return PCH_JSP;

	default:

		return PCH_NONE;

	}

drivers/gpu/drm/i915/intel_pch.h

+4 −1
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ enum intel_pch { 
	PCH_SPT,        /* Sunrisepoint/Kaby Lake PCH */

	PCH_CNP,        /* Cannon/Comet Lake PCH */

	PCH_ICP,	/* Ice Lake PCH */

	PCH_JSP,	/* Jasper Lake PCH */

	PCH_MCC,        /* Mule Creek Canyon PCH */

	PCH_TGP,	/* Tiger Lake PCH */

};
@@ -44,14 +45,16 @@ enum intel_pch { 
#define INTEL_PCH_CMP2_DEVICE_ID_TYPE		0x0680

#define INTEL_PCH_ICP_DEVICE_ID_TYPE		0x3480

#define INTEL_PCH_MCC_DEVICE_ID_TYPE		0x4B00

#define INTEL_PCH_MCC2_DEVICE_ID_TYPE		0x3880

#define INTEL_PCH_TGP_DEVICE_ID_TYPE		0xA080

#define INTEL_PCH_JSP_DEVICE_ID_TYPE		0x4D80

#define INTEL_PCH_JSP2_DEVICE_ID_TYPE		0x3880

#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100

#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000

#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */



#define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)

#define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)

#define HAS_PCH_JSP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_JSP)

#define HAS_PCH_MCC(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MCC)

#define HAS_PCH_TGP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_TGP)

#define HAS_PCH_ICP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ICP)