Commit 94329ce6 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

dt-bindings: clock: Add Qcom SM6375 GPUCC 



Add device tree bindings for graphics clock controller for Qualcomm
Technology Inc's SM6375 SoCs.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208091340.124641-8-konrad.dybcio@linaro.org
parent a5b9c5c5

Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml

0 → 100644
+60 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Graphics Clock & Reset Controller on SM6375



maintainers:

  - Konrad Dybcio <konrad.dybcio@linaro.org>



description: |

  Qualcomm graphics clock control module provides clocks, resets and power

  domains on Qualcomm SoCs.



  See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h



properties:

  compatible:

    enum:

      - qcom,sm6375-gpucc



  clocks:

    items:

      - description: Board XO source

      - description: GPLL0 main branch source

      - description: GPLL0 div branch source

      - description: SNoC DVM GFX source



required:

  - compatible

  - clocks



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,sm6375-gcc.h>

    #include <dt-bindings/clock/qcom,rpmcc.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        clock-controller@5990000 {

            compatible = "qcom,sm6375-gpucc";

            reg = <0 0x05990000 0 0x9000>;

            clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,

                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,

                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,

                     <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;

            #clock-cells = <1>;

            #reset-cells = <1>;

            #power-domain-cells = <1>;

        };

    };

...

include/dt-bindings/clock/qcom,sm6375-gpucc.h

0 → 100644
+36 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2021, The Linux Foundation. All rights reserved.

 * Copyright (c) 2023, Linaro Limited

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H

#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H



/* GPU CC clocks */

#define GPU_CC_PLL0					0

#define GPU_CC_PLL1					1

#define GPU_CC_AHB_CLK					2

#define GPU_CC_CX_GFX3D_CLK				3

#define GPU_CC_CX_GFX3D_SLV_CLK				4

#define GPU_CC_CX_GMU_CLK				5

#define GPU_CC_CX_SNOC_DVM_CLK				6

#define GPU_CC_CXO_AON_CLK				7

#define GPU_CC_CXO_CLK					8

#define GPU_CC_GMU_CLK_SRC				9

#define GPU_CC_GX_CXO_CLK				10

#define GPU_CC_GX_GFX3D_CLK				11

#define GPU_CC_GX_GFX3D_CLK_SRC				12

#define GPU_CC_GX_GMU_CLK				13

#define GPU_CC_SLEEP_CLK				14



/* GDSCs */

#define GPU_CX_GDSC					0

#define GPU_GX_GDSC					1



/* Resets */

#define GPU_GX_BCR					0

#define GPU_ACD_BCR					1

#define GPU_GX_ACD_MISC_BCR				2



#endif