Commit 93e220a6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 

Pull crypto updates from Herbert Xu:
 "API:
   - hwrng core now credits for low-quality RNG devices.

  Algorithms:
   - Optimisations for neon aes on arm/arm64.
   - Add accelerated crc32_be on arm64.
   - Add ffdheXYZ(dh) templates.
   - Disallow hmac keys < 112 bits in FIPS mode.
   - Add AVX assembly implementation for sm3 on x86.

  Drivers:
   - Add missing local_bh_disable calls for crypto_engine callback.
   - Ensure BH is disabled in crypto_engine callback path.
   - Fix zero length DMA mappings in ccree.
   - Add synchronization between mailbox accesses in octeontx2.
   - Add Xilinx SHA3 driver.
   - Add support for the TDES IP available on sama7g5 SoC in atmel"

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (137 commits)
  crypto: xilinx - Turn SHA into a tristate and allow COMPILE_TEST
  MAINTAINERS: update HPRE/SEC2/TRNG driver maintainers list
  crypto: dh - Remove the unused function dh_safe_prime_dh_alg()
  hwrng: nomadik - Change clk_disable to clk_disable_unprepare
  crypto: arm64 - cleanup comments
  crypto: qat - fix initialization of pfvf rts_map_msg structures
  crypto: qat - fix initialization of pfvf cap_msg structures
  crypto: qat - remove unneeded assignment
  crypto: qat - disable registration of algorithms
  crypto: hisilicon/qm - fix memset during queues clearing
  crypto: xilinx: prevent probing on non-xilinx hardware
  crypto: marvell/octeontx - Use swap() instead of open coding it
  crypto: ccree - Fix use after free in cc_cipher_exit()
  crypto: ccp - ccp_dmaengine_unregister release dma channels
  crypto: octeontx2 - fix missing unlock
  hwrng: cavium - fix NULL but dereferenced coccicheck error
  crypto: cavium/nitrox - don't cast parameter in bit operations
  crypto: vmx - add missing dependencies
  MAINTAINERS: Add maintainer for Xilinx ZynqMP SHA3 driver
  crypto: xilinx - Add Xilinx SHA3 driver
  ...
parents 5628b8de 0e03b8fd

Documentation/ABI/testing/debugfs-hisi-hpre

+94 −84
Original line number Diff line number Diff line
@@ -27,6 +27,16 @@ Description: One HPRE controller has one PF and multiple VFs, each function 
		has a QM. Select the QM which below qm refers to.

		Only available for PF.



What:		/sys/kernel/debug/hisi_hpre/<bdf>/alg_qos

Date:		Jun 2021

Contact:	linux-crypto@vger.kernel.org

Description:	The <bdf> is related the function for PF and VF.

		HPRE driver supports to configure each function's QoS, the driver

		supports to write <bdf> value to alg_qos in the host. Such as

		"echo <bdf> value > alg_qos". The qos value is 1~1000, means

		1/1000~1000/1000 of total QoS. The driver reading alg_qos to

		get related QoS in the host and VM, Such as "cat alg_qos".



What:		/sys/kernel/debug/hisi_hpre/<bdf>/regs

Date:		Sep 2019

Contact:	linux-crypto@vger.kernel.org

Documentation/ABI/testing/debugfs-hisi-sec

+78 −68
Original line number Diff line number Diff line
@@ -14,6 +14,16 @@ Description: One SEC controller has one PF and multiple VFs, each function 
		qm refers to.

		Only available for PF.



What:		/sys/kernel/debug/hisi_sec2/<bdf>/alg_qos

Date:		Jun 2021

Contact:	linux-crypto@vger.kernel.org

Description:	The <bdf> is related the function for PF and VF.

		SEC driver supports to configure each function's QoS, the driver

		supports to write <bdf> value to alg_qos in the host. Such as

		"echo <bdf> value > alg_qos". The qos value is 1~1000, means

		1/1000~1000/1000 of total QoS. The driver reading alg_qos to

		get related QoS in the host and VM, Such as "cat alg_qos".



What:		/sys/kernel/debug/hisi_sec2/<bdf>/qm/qm_regs

Date:		Oct 2019

Contact:	linux-crypto@vger.kernel.org

Documentation/ABI/testing/debugfs-hisi-zip

+78 −68
Original line number Diff line number Diff line
@@ -26,6 +26,16 @@ Description: One ZIP controller has one PF and multiple VFs, each function 
		has a QM. Select the QM which below qm refers to.

		Only available for PF.



What:		/sys/kernel/debug/hisi_zip/<bdf>/alg_qos

Date:		Jun 2021

Contact:	linux-crypto@vger.kernel.org

Description:	The <bdf> is related the function for PF and VF.

		ZIP driver supports to configure each function's QoS, the driver

		supports to write <bdf> value to alg_qos in the host. Such as

		"echo <bdf> value > alg_qos". The qos value is 1~1000, means

		1/1000~1000/1000 of total QoS. The driver reading alg_qos to

		get related QoS in the host and VM, Such as "cat alg_qos".



What:		/sys/kernel/debug/hisi_zip/<bdf>/qm/regs

Date:		Nov 2018

Contact:	linux-crypto@vger.kernel.org

MAINTAINERS

+8 −3
Original line number Diff line number Diff line
@@ -8644,7 +8644,7 @@ S: Maintained 
F:	drivers/gpio/gpio-hisi.c









HISILICON HIGH PERFORMANCE RSA ENGINE DRIVER (HPRE)









M:	Zaibo Xu <xuzaibo@huawei.com>









M:	Longfang Liu <liulongfang@huawei.com>









L:	linux-crypto@vger.kernel.org









S:	Maintained









F:	Documentation/ABI/testing/debugfs-hisi-hpre








@@ -8724,8 +8724,8 @@ F:	Documentation/devicetree/bindings/scsi/hisilicon-sas.txt







F:	drivers/scsi/hisi_sas/

















HISILICON SECURITY ENGINE V2 DRIVER (SEC2)









M:	Zaibo Xu <xuzaibo@huawei.com>









M:	Kai Ye <yekai13@huawei.com>









M:	Longfang Liu <liulongfang@huawei.com>









L:	linux-crypto@vger.kernel.org









S:	Maintained









F:	Documentation/ABI/testing/debugfs-hisi-sec








@@ -8756,7 +8756,7 @@ F:	Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml







F:	drivers/mfd/hi6421-spmi-pmic.c

















HISILICON TRUE RANDOM NUMBER GENERATOR V2 SUPPORT









M:	Zaibo Xu <xuzaibo@huawei.com>









M:	Weili Qian <qianweili@huawei.com>









S:	Maintained









F:	drivers/crypto/hisilicon/trng/trng.c
















@@ -21302,6 +21302,11 @@ T:	git https://github.com/Xilinx/linux-xlnx.git







F:	Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml









F:	drivers/phy/xilinx/phy-zynqmp.c

















XILINX ZYNQMP SHA3 DRIVER









M:	Harsha <harsha.harsha@xilinx.com>









S:	Maintained









F:	drivers/crypto/xilinx/zynqmp-sha.c

















XILINX EVENT MANAGEMENT DRIVER









M:	Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>









S:	Maintained

























arch/alpha/include/asm/xor.h



+36
−17






























Original line number
Diff line number
Diff line







@@ -5,24 +5,43 @@







 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6









 */



















extern void xor_alpha_2(unsigned long, unsigned long *, unsigned long *);









extern void xor_alpha_3(unsigned long, unsigned long *, unsigned long *,









		        unsigned long *);









extern void xor_alpha_4(unsigned long, unsigned long *, unsigned long *,









		        unsigned long *, unsigned long *);









extern void xor_alpha_5(unsigned long, unsigned long *, unsigned long *,









		        unsigned long *, unsigned long *, unsigned long *);









extern void









xor_alpha_2(unsigned long bytes, unsigned long * __restrict p1,









	    const unsigned long * __restrict p2);









extern void









xor_alpha_3(unsigned long bytes, unsigned long * __restrict p1,









	    const unsigned long * __restrict p2,









	    const unsigned long * __restrict p3);









extern void









xor_alpha_4(unsigned long bytes, unsigned long * __restrict p1,









	    const unsigned long * __restrict p2,









	    const unsigned long * __restrict p3,









	    const unsigned long * __restrict p4);









extern void









xor_alpha_5(unsigned long bytes, unsigned long * __restrict p1,









	    const unsigned long * __restrict p2,









	    const unsigned long * __restrict p3,









	    const unsigned long * __restrict p4,









	    const unsigned long * __restrict p5);



















extern void xor_alpha_prefetch_2(unsigned long, unsigned long *,









				 unsigned long *);









extern void xor_alpha_prefetch_3(unsigned long, unsigned long *,









				 unsigned long *, unsigned long *);









extern void xor_alpha_prefetch_4(unsigned long, unsigned long *,









				 unsigned long *, unsigned long *,









				 unsigned long *);









extern void xor_alpha_prefetch_5(unsigned long, unsigned long *,









				 unsigned long *, unsigned long *,









				 unsigned long *, unsigned long *);









extern void









xor_alpha_prefetch_2(unsigned long bytes, unsigned long * __restrict p1,









		     const unsigned long * __restrict p2);









extern void









xor_alpha_prefetch_3(unsigned long bytes, unsigned long * __restrict p1,









		     const unsigned long * __restrict p2,









		     const unsigned long * __restrict p3);









extern void









xor_alpha_prefetch_4(unsigned long bytes, unsigned long * __restrict p1,









		     const unsigned long * __restrict p2,









		     const unsigned long * __restrict p3,









		     const unsigned long * __restrict p4);









extern void









xor_alpha_prefetch_5(unsigned long bytes, unsigned long * __restrict p1,









		     const unsigned long * __restrict p2,









		     const unsigned long * __restrict p3,









		     const unsigned long * __restrict p4,









		     const unsigned long * __restrict p5);



















asm("								\n\









	.text							\n\