Commit 93cebeb1 authored by Marco Chiappero's avatar Marco Chiappero Committed by Herbert Xu
Browse files

crypto: qat - add capability detection logic in qat_4xxx 



Add logic to detect device capabilities in qat_4xxx driver.

Read fuses and build the device capabilities mask. This will enable
services and handling specific to QAT 4xxx devices.

Co-developed-by: default avatarTomaszx Kowalik <tomaszx.kowalik@intel.com>
Signed-off-by: default avatarTomaszx Kowalik <tomaszx.kowalik@intel.com>
Signed-off-by: default avatarMarco Chiappero <marco.chiappero@intel.com>
Reviewed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 5106dfea

drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c

+24 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
#include <adf_pf2vf_msg.h>

#include <adf_gen4_hw_data.h>

#include "adf_4xxx_hw_data.h"

#include "icp_qat_hw.h"



struct adf_fw_config {

	u32 ae_mask;
@@ -91,6 +92,28 @@ static void set_msix_default_rttable(struct adf_accel_dev *accel_dev) 
		ADF_CSR_WR(csr, ADF_4XXX_MSIX_RTTABLE_OFFSET(i), i);

}



static u32 get_accel_cap(struct adf_accel_dev *accel_dev)

{

	struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;

	u32 fusectl1;

	u32 capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |

			   ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |

			   ICP_ACCEL_CAPABILITIES_AUTHENTICATION |

			   ICP_ACCEL_CAPABILITIES_AES_V2;



	/* Read accelerator capabilities mask */

	pci_read_config_dword(pdev, ADF_4XXX_FUSECTL1_OFFSET, &fusectl1);



	if (fusectl1 & ICP_ACCEL_4XXX_MASK_CIPHER_SLICE)

		capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;

	if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE)

		capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;

	if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE)

		capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;



	return capabilities;

}



static enum dev_sku_info get_sku(struct adf_hw_device_data *self)

{

	return DEV_SKU_1;
@@ -189,6 +212,7 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data) 
	hw_data->get_misc_bar_id = get_misc_bar_id;

	hw_data->get_arb_info = get_arb_info;

	hw_data->get_admin_info = get_admin_info;

	hw_data->get_accel_cap = get_accel_cap;

	hw_data->get_sku = get_sku;

	hw_data->fw_name = ADF_4XXX_FW;

	hw_data->fw_mmp_name = ADF_4XXX_MMP;

drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.h

+11 −0
Original line number Diff line number Diff line
@@ -69,6 +69,17 @@ 
#define ADF_4XXX_ASYM_OBJ	"qat_4xxx_asym.bin"

#define ADF_4XXX_ADMIN_OBJ	"qat_4xxx_admin.bin"



/* qat_4xxx fuse bits are different from old GENs, redefine them */

enum icp_qat_4xxx_slice_mask {

	ICP_ACCEL_4XXX_MASK_CIPHER_SLICE = BIT(0),

	ICP_ACCEL_4XXX_MASK_AUTH_SLICE = BIT(1),

	ICP_ACCEL_4XXX_MASK_PKE_SLICE = BIT(2),

	ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE = BIT(3),

	ICP_ACCEL_4XXX_MASK_UCS_SLICE = BIT(4),

	ICP_ACCEL_4XXX_MASK_EIA3_SLICE = BIT(5),

	ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(6),

};



void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data);

void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data);

drivers/crypto/qat/qat_4xxx/adf_drv.c

+3 −0
Original line number Diff line number Diff line
@@ -233,6 +233,9 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 
		pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));

	}



	/* Get accelerator capabilities mask */

	hw_data->accel_capabilities_mask = hw_data->get_accel_cap(accel_dev);



	/* Find and map all the device's BARS */

	bar_mask = pci_select_bars(pdev, IORESOURCE_MEM) & ADF_4XXX_BAR_MASK;