Commit 93c66b40 authored by Quentin Perret's avatar Quentin Perret Committed by Marc Zyngier
Browse files

KVM: arm64: Add support for stage-2 cache flushing in generic page-table 



Add support for cache flushing a range of the stage-2 address space to
the generic page-table code.

Signed-off-by: default avatarQuentin Perret <qperret@google.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Reviewed-by: default avatarGavin Shan <gshan@redhat.com>
Cc: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200911132529.19844-15-will@kernel.org
parent cc38d61c

arch/arm64/include/asm/kvm_pgtable.h

+15 −0
Original line number Diff line number Diff line
@@ -248,6 +248,21 @@ kvm_pte_t kvm_pgtable_stage2_mkold(struct kvm_pgtable *pgt, u64 addr); 
 */

bool kvm_pgtable_stage2_is_young(struct kvm_pgtable *pgt, u64 addr);



/**

 * kvm_pgtable_stage2_flush_range() - Clean and invalidate data cache to Point

 * 				      of Coherency for guest stage-2 address

 *				      range.

 * @pgt:	Page-table structure initialised by kvm_pgtable_stage2_init().

 * @addr:	Intermediate physical address from which to flush.

 * @size:	Size of the range.

 *

 * The offset of @addr within a page is ignored and @size is rounded-up to

 * the next page boundary.

 *

 * Return: 0 on success, negative error code on failure.

 */

int kvm_pgtable_stage2_flush(struct kvm_pgtable *pgt, u64 addr, u64 size);



/**

 * kvm_pgtable_walk() - Walk a page-table.

 * @pgt:	Page-table structure initialised by kvm_pgtable_*_init().

arch/arm64/kvm/hyp/pgtable.c

+26 −0
Original line number Diff line number Diff line
@@ -782,6 +782,32 @@ bool kvm_pgtable_stage2_is_young(struct kvm_pgtable *pgt, u64 addr) 
	return pte & KVM_PTE_LEAF_ATTR_LO_S2_AF;

}



static int stage2_flush_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep,

			       enum kvm_pgtable_walk_flags flag,

			       void * const arg)

{

	kvm_pte_t pte = *ptep;



	if (!kvm_pte_valid(pte) || !stage2_pte_cacheable(pte))

		return 0;



	stage2_flush_dcache(kvm_pte_follow(pte), kvm_granule_size(level));

	return 0;

}



int kvm_pgtable_stage2_flush(struct kvm_pgtable *pgt, u64 addr, u64 size)

{

	struct kvm_pgtable_walker walker = {

		.cb	= stage2_flush_walker,

		.flags	= KVM_PGTABLE_WALK_LEAF,

	};



	if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))

		return 0;



	return kvm_pgtable_walk(pgt, addr, size, &walker);

}



int kvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm *kvm)

{

	size_t pgd_sz;