Loading Documentation/filesystems/xfs.txt +3 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,9 @@ When mounting an XFS filesystem, the following options are accepted. removing extended attributes) the on-disk superblock feature bit field will be updated to reflect this format being in use. CRC enabled filesystems always use the attr2 format, and so will reject the noattr2 mount option if it is set. barrier Enables the use of block layer write barriers for writes into the journal and unwritten extent conversion. This allows for Loading arch/arm/include/asm/tlb.h +4 −23 Original line number Diff line number Diff line Loading @@ -33,18 +33,6 @@ #include <asm/pgalloc.h> #include <asm/tlbflush.h> /* * We need to delay page freeing for SMP as other CPUs can access pages * which have been removed but not yet had their TLB entries invalidated. * Also, as ARMv7 speculative prefetch can drag new entries into the TLB, * we need to apply this same delaying tactic to ensure correct operation. */ #if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7) #define tlb_fast_mode(tlb) 0 #else #define tlb_fast_mode(tlb) 1 #endif #define MMU_GATHER_BUNDLE 8 /* Loading Loading @@ -112,13 +100,11 @@ static inline void __tlb_alloc_page(struct mmu_gather *tlb) static inline void tlb_flush_mmu(struct mmu_gather *tlb) { tlb_flush(tlb); if (!tlb_fast_mode(tlb)) { free_pages_and_swap_cache(tlb->pages, tlb->nr); tlb->nr = 0; if (tlb->pages == tlb->local) __tlb_alloc_page(tlb); } } static inline void tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int fullmm) Loading Loading @@ -178,11 +164,6 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma) static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page) { if (tlb_fast_mode(tlb)) { free_page_and_swap_cache(page); return 1; /* avoid calling tlb_flush_mmu */ } tlb->pages[tlb->nr++] = page; VM_BUG_ON(tlb->nr > tlb->max); return tlb->max - tlb->nr; Loading arch/ia64/include/asm/tlb.h +8 −33 Original line number Diff line number Diff line Loading @@ -46,12 +46,6 @@ #include <asm/tlbflush.h> #include <asm/machvec.h> #ifdef CONFIG_SMP # define tlb_fast_mode(tlb) ((tlb)->nr == ~0U) #else # define tlb_fast_mode(tlb) (1) #endif /* * If we can't allocate a page to make a big batch of page pointers * to work on, then just handle a few from the on-stack structure. Loading @@ -60,7 +54,7 @@ struct mmu_gather { struct mm_struct *mm; unsigned int nr; /* == ~0U => fast mode */ unsigned int nr; unsigned int max; unsigned char fullmm; /* non-zero means full mm flush */ unsigned char need_flush; /* really unmapped some PTEs? */ Loading Loading @@ -103,6 +97,7 @@ extern struct ia64_tr_entry *ia64_idtrs[NR_CPUS]; static inline void ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end) { unsigned long i; unsigned int nr; if (!tlb->need_flush) Loading Loading @@ -141,14 +136,12 @@ ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long e /* lastly, release the freed pages */ nr = tlb->nr; if (!tlb_fast_mode(tlb)) { unsigned long i; tlb->nr = 0; tlb->start_addr = ~0UL; for (i = 0; i < nr; ++i) free_page_and_swap_cache(tlb->pages[i]); } } static inline void __tlb_alloc_page(struct mmu_gather *tlb) { Loading @@ -167,20 +160,7 @@ tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int full_m tlb->mm = mm; tlb->max = ARRAY_SIZE(tlb->local); tlb->pages = tlb->local; /* * Use fast mode if only 1 CPU is online. * * It would be tempting to turn on fast-mode for full_mm_flush as well. But this * doesn't work because of speculative accesses and software prefetching: the page * table of "mm" may (and usually is) the currently active page table and even * though the kernel won't do any user-space accesses during the TLB shoot down, a * compiler might use speculation or lfetch.fault on what happens to be a valid * user-space address. This in turn could trigger a TLB miss fault (or a VHPT * walk) and re-insert a TLB entry we just removed. Slow mode avoids such * problems. (We could make fast-mode work by switching the current task to a * different "mm" during the shootdown.) --davidm 08/02/2002 */ tlb->nr = (num_online_cpus() == 1) ? ~0U : 0; tlb->nr = 0; tlb->fullmm = full_mm_flush; tlb->start_addr = ~0UL; } Loading Loading @@ -214,11 +194,6 @@ static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page) { tlb->need_flush = 1; if (tlb_fast_mode(tlb)) { free_page_and_swap_cache(page); return 1; /* avoid calling tlb_flush_mmu */ } if (!tlb->nr && tlb->pages == tlb->local) __tlb_alloc_page(tlb); Loading arch/x86/pci/common.c +4 −1 Original line number Diff line number Diff line Loading @@ -628,7 +628,9 @@ int pcibios_add_device(struct pci_dev *dev) pa_data = boot_params.hdr.setup_data; while (pa_data) { data = phys_to_virt(pa_data); data = ioremap(pa_data, sizeof(*rom)); if (!data) return -ENOMEM; if (data->type == SETUP_PCI) { rom = (struct pci_setup_rom *)data; Loading @@ -645,6 +647,7 @@ int pcibios_add_device(struct pci_dev *dev) } } pa_data = data->next; iounmap(data); } return 0; } Loading drivers/iio/buffer_cb.c +4 −1 Original line number Diff line number Diff line Loading @@ -64,7 +64,7 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev, while (chan->indio_dev) { if (chan->indio_dev != indio_dev) { ret = -EINVAL; goto error_release_channels; goto error_free_scan_mask; } set_bit(chan->channel->scan_index, cb_buff->buffer.scan_mask); Loading @@ -73,6 +73,8 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev, return cb_buff; error_free_scan_mask: kfree(cb_buff->buffer.scan_mask); error_release_channels: iio_channel_release_all(cb_buff->channels); error_free_cb_buff: Loading Loading @@ -100,6 +102,7 @@ EXPORT_SYMBOL_GPL(iio_channel_stop_all_cb); void iio_channel_release_all_cb(struct iio_cb_buffer *cb_buff) { kfree(cb_buff->buffer.scan_mask); iio_channel_release_all(cb_buff->channels); kfree(cb_buff); } Loading Loading
Documentation/filesystems/xfs.txt +3 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,9 @@ When mounting an XFS filesystem, the following options are accepted. removing extended attributes) the on-disk superblock feature bit field will be updated to reflect this format being in use. CRC enabled filesystems always use the attr2 format, and so will reject the noattr2 mount option if it is set. barrier Enables the use of block layer write barriers for writes into the journal and unwritten extent conversion. This allows for Loading
arch/arm/include/asm/tlb.h +4 −23 Original line number Diff line number Diff line Loading @@ -33,18 +33,6 @@ #include <asm/pgalloc.h> #include <asm/tlbflush.h> /* * We need to delay page freeing for SMP as other CPUs can access pages * which have been removed but not yet had their TLB entries invalidated. * Also, as ARMv7 speculative prefetch can drag new entries into the TLB, * we need to apply this same delaying tactic to ensure correct operation. */ #if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7) #define tlb_fast_mode(tlb) 0 #else #define tlb_fast_mode(tlb) 1 #endif #define MMU_GATHER_BUNDLE 8 /* Loading Loading @@ -112,13 +100,11 @@ static inline void __tlb_alloc_page(struct mmu_gather *tlb) static inline void tlb_flush_mmu(struct mmu_gather *tlb) { tlb_flush(tlb); if (!tlb_fast_mode(tlb)) { free_pages_and_swap_cache(tlb->pages, tlb->nr); tlb->nr = 0; if (tlb->pages == tlb->local) __tlb_alloc_page(tlb); } } static inline void tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int fullmm) Loading Loading @@ -178,11 +164,6 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma) static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page) { if (tlb_fast_mode(tlb)) { free_page_and_swap_cache(page); return 1; /* avoid calling tlb_flush_mmu */ } tlb->pages[tlb->nr++] = page; VM_BUG_ON(tlb->nr > tlb->max); return tlb->max - tlb->nr; Loading
arch/ia64/include/asm/tlb.h +8 −33 Original line number Diff line number Diff line Loading @@ -46,12 +46,6 @@ #include <asm/tlbflush.h> #include <asm/machvec.h> #ifdef CONFIG_SMP # define tlb_fast_mode(tlb) ((tlb)->nr == ~0U) #else # define tlb_fast_mode(tlb) (1) #endif /* * If we can't allocate a page to make a big batch of page pointers * to work on, then just handle a few from the on-stack structure. Loading @@ -60,7 +54,7 @@ struct mmu_gather { struct mm_struct *mm; unsigned int nr; /* == ~0U => fast mode */ unsigned int nr; unsigned int max; unsigned char fullmm; /* non-zero means full mm flush */ unsigned char need_flush; /* really unmapped some PTEs? */ Loading Loading @@ -103,6 +97,7 @@ extern struct ia64_tr_entry *ia64_idtrs[NR_CPUS]; static inline void ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end) { unsigned long i; unsigned int nr; if (!tlb->need_flush) Loading Loading @@ -141,14 +136,12 @@ ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long e /* lastly, release the freed pages */ nr = tlb->nr; if (!tlb_fast_mode(tlb)) { unsigned long i; tlb->nr = 0; tlb->start_addr = ~0UL; for (i = 0; i < nr; ++i) free_page_and_swap_cache(tlb->pages[i]); } } static inline void __tlb_alloc_page(struct mmu_gather *tlb) { Loading @@ -167,20 +160,7 @@ tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int full_m tlb->mm = mm; tlb->max = ARRAY_SIZE(tlb->local); tlb->pages = tlb->local; /* * Use fast mode if only 1 CPU is online. * * It would be tempting to turn on fast-mode for full_mm_flush as well. But this * doesn't work because of speculative accesses and software prefetching: the page * table of "mm" may (and usually is) the currently active page table and even * though the kernel won't do any user-space accesses during the TLB shoot down, a * compiler might use speculation or lfetch.fault on what happens to be a valid * user-space address. This in turn could trigger a TLB miss fault (or a VHPT * walk) and re-insert a TLB entry we just removed. Slow mode avoids such * problems. (We could make fast-mode work by switching the current task to a * different "mm" during the shootdown.) --davidm 08/02/2002 */ tlb->nr = (num_online_cpus() == 1) ? ~0U : 0; tlb->nr = 0; tlb->fullmm = full_mm_flush; tlb->start_addr = ~0UL; } Loading Loading @@ -214,11 +194,6 @@ static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page) { tlb->need_flush = 1; if (tlb_fast_mode(tlb)) { free_page_and_swap_cache(page); return 1; /* avoid calling tlb_flush_mmu */ } if (!tlb->nr && tlb->pages == tlb->local) __tlb_alloc_page(tlb); Loading
arch/x86/pci/common.c +4 −1 Original line number Diff line number Diff line Loading @@ -628,7 +628,9 @@ int pcibios_add_device(struct pci_dev *dev) pa_data = boot_params.hdr.setup_data; while (pa_data) { data = phys_to_virt(pa_data); data = ioremap(pa_data, sizeof(*rom)); if (!data) return -ENOMEM; if (data->type == SETUP_PCI) { rom = (struct pci_setup_rom *)data; Loading @@ -645,6 +647,7 @@ int pcibios_add_device(struct pci_dev *dev) } } pa_data = data->next; iounmap(data); } return 0; } Loading
drivers/iio/buffer_cb.c +4 −1 Original line number Diff line number Diff line Loading @@ -64,7 +64,7 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev, while (chan->indio_dev) { if (chan->indio_dev != indio_dev) { ret = -EINVAL; goto error_release_channels; goto error_free_scan_mask; } set_bit(chan->channel->scan_index, cb_buff->buffer.scan_mask); Loading @@ -73,6 +73,8 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev, return cb_buff; error_free_scan_mask: kfree(cb_buff->buffer.scan_mask); error_release_channels: iio_channel_release_all(cb_buff->channels); error_free_cb_buff: Loading Loading @@ -100,6 +102,7 @@ EXPORT_SYMBOL_GPL(iio_channel_stop_all_cb); void iio_channel_release_all_cb(struct iio_cb_buffer *cb_buff) { kfree(cb_buff->buffer.scan_mask); iio_channel_release_all(cb_buff->channels); kfree(cb_buff); } Loading