Commit 93929fb6 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'asm-generic-mmiotrace' into asm-generic 

A patch series from Sai Prakash Ranjan, who explains:

Generic MMIO read/write i.e., __raw_{read,write}{b,l,w,q} accessors
are typically used to read/write from/to memory mapped registers
and can cause hangs or some undefined behaviour in following cases,

* If the access to the register space is unclocked, for example: if
  there is an access to multimedia(MM) block registers without MM
  clocks.

* If the register space is protected and not set to be accessible from
  non-secure world, for example: only EL3 (EL: Exception level) access
  is allowed and any EL2/EL1 access is forbidden.

* If xPU(memory/register protection units) is controlling access to
  certain memory/register space for specific clients.

and more...

Such cases usually results in instant reboot/SErrors/NOC or interconnect
hangs and tracing these register accesses can be very helpful to debug
such issues during initial development stages and also in later stages.

So use ftrace trace events to log such MMIO register accesses which
provides rich feature set such as early enablement of trace events,
filtering capability, dumping ftrace logs on console and many more.

Sample output:

rwmmio_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
rwmmio_post_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
rwmmio_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 addr=0xfffffbfffdbff610
rwmmio_post_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 val=0x0 addr=0xfffffbfffdbff610

This series is a follow-up for the series [1] and a recent series [2] making use
of both.

[1] https://lore.kernel.org/lkml/cover.1536430404.git.saiprakash.ranjan@codeaurora.org/
[2] https://lore.kernel.org/lkml/1604631386-178312-1-git-send-email-psodagud@codeaurora.org/

Note in v4 version, Arnd suggested to benchmark and compare size with callback
based implementation, please see [3] for more details on that with brief comparison below.

**Inline version with CONFIG_FTRACE=y and CONFIG_TRACE_MMIO_ACCESS=y**
$ size vmlinux
   text           data             bss     dec             hex         filename
 23884219        14284468         532568 38701255        24e88c7        vmlinux

**Callback version with CONFIG_FTRACE=y and CONFIG_TRACE_MMIO_ACCESS=y**
$ size vmlinux
    text          data             bss     dec             hex        filename
 24108179        14279596         532568 38920343        251e097       vmlinux

$ ./scripts/bloat-o-meter inline-vmlinux callback-vmlinux
add/remove: 8/3 grow/shrink: 4889/89 up/down: 242244/-11564 (230680)
Total: Before=25812612, After=26043292, chg +0.89%

[3] https://lore.kernel.org/lkml/466449a1-36da-aaa9-7e4f-477f36b52c9e@quicinc.com/

Link: https://lore.kernel.org/lkml/cover.1652891705.git.quic_saipraka@quicinc.com/

* asm-generic-mmiotrace:
  soc: qcom: geni: Disable MMIO tracing for GENI SE
  serial: qcom_geni_serial: Disable MMIO tracing for geni serial
  asm-generic/io: Add logging support for MMIO accessors
  KVM: arm64: Add a flag to disable MMIO trace for nVHE KVM
  lib: Add register read/write tracing support
  drm/meson: Fix overflow implicit truncation warnings
  irqchip/tegra: Fix overflow implicit truncation warnings
  coresight: etm4x: Use asm-generic IO memory barriers
  arm64: io: Use asm-generic high level MMIO accessors
  arch/*: Disable softirq stacks on PREEMPT_RT.
parents b13baccc 6f1de1da

arch/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -1396,6 +1396,9 @@ config ARCH_HAS_ELFCORE_COMPAT 
config ARCH_HAS_PARANOID_L1D_FLUSH

	bool



config ARCH_HAVE_TRACE_MMIO_ACCESS

	bool



config DYNAMIC_SIGFRAME

	bool

arch/arm/kernel/irq.c

+2 −1
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ static void __init init_irq_stacks(void) 
	}

}



#ifndef CONFIG_PREEMPT_RT

static void ____do_softirq(void *arg)

{

	__do_softirq();
@@ -80,7 +81,7 @@ void do_softirq_own_stack(void) 
	call_with_stack(____do_softirq, NULL,

			__this_cpu_read(irq_stack_ptr));

}



#endif

#endif



int arch_show_interrupts(struct seq_file *p, int prec)

arch/arm64/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ config ARM64 
	select ARCH_HAS_ZONE_DMA_SET if EXPERT

	select ARCH_HAVE_ELF_PROT

	select ARCH_HAVE_NMI_SAFE_CMPXCHG

	select ARCH_HAVE_TRACE_MMIO_ACCESS

	select ARCH_INLINE_READ_LOCK if !PREEMPTION

	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION

	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION

arch/arm64/include/asm/io.h

+8 −33
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) 
}



/* IO barriers */

#define __iormb(v)							\

#define __io_ar(v)							\

({									\

	unsigned long tmp;						\

									\
@@ -108,39 +108,14 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) 
		     : "memory");					\

})



#define __io_par(v)		__iormb(v)

#define __iowmb()		dma_wmb()

#define __iomb()		dma_mb()



/*

 * Relaxed I/O memory access primitives. These follow the Device memory

 * ordering rules but do not guarantee any ordering relative to Normal memory

 * accesses.

 */

#define readb_relaxed(c)	({ u8  __r = __raw_readb(c); __r; })

#define readw_relaxed(c)	({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })

#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })

#define readq_relaxed(c)	({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })

#define __io_bw()		dma_wmb()

#define __io_br(v)

#define __io_aw(v)



#define writeb_relaxed(v,c)	((void)__raw_writeb((v),(c)))

#define writew_relaxed(v,c)	((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))

#define writel_relaxed(v,c)	((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))

#define writeq_relaxed(v,c)	((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))



/*

 * I/O memory access primitives. Reads are ordered relative to any

 * following Normal memory access. Writes are ordered relative to any prior

 * Normal memory access.

 */

#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(__v); __v; })

#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(__v); __v; })

#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })

#define readq(c)		({ u64 __v = readq_relaxed(c); __iormb(__v); __v; })



#define writeb(v,c)		({ __iowmb(); writeb_relaxed((v),(c)); })

#define writew(v,c)		({ __iowmb(); writew_relaxed((v),(c)); })

#define writel(v,c)		({ __iowmb(); writel_relaxed((v),(c)); })

#define writeq(v,c)		({ __iowmb(); writeq_relaxed((v),(c)); })

/* arm64-specific, don't use in portable drivers */

#define __iormb(v)		__io_ar(v)

#define __iowmb()		__io_bw()

#define __iomb()		dma_mb()



/*

 *  I/O port access primitives.

arch/arm64/kvm/hyp/nvhe/Makefile

+6 −1
Original line number Diff line number Diff line
@@ -4,7 +4,12 @@ 
#



asflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS

ccflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS



# Tracepoint and MMIO logging symbols should not be visible at nVHE KVM as

# there is no way to execute them and any such MMIO access from nVHE KVM

# will explode instantly (Words of Marc Zyngier). So introduce a generic flag

# __DISABLE_TRACE_MMIO__ to disable MMIO tracing for nVHE KVM.

ccflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS -D__DISABLE_TRACE_MMIO__



hostprogs := gen-hyprel

HOST_EXTRACFLAGS += -I$(objtree)/include