Commit 938c778f authored by John Harrison's avatar John Harrison Committed by Matt Roper
Browse files

drm/i915/xehp: Extra media engines - Part 1 (engine definitions) 



Xe_HP can have a lot of extra media engines. This patch adds the basic
definitions for them.

v2:
 - Re-order intel_gt_info and intel_device_info slightly to avoid
   unnecessary padding now that we've increased the size of
   intel_engine_mask_t.  (Tvrtko)
v3:
 - Drop the .hw_id assignments.  (Lucas)
v4:
 - Fix graphics_ver typo for VCS4 (should be 12, not 11).  (Lucas)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723191024.1553405-1-matthew.d.roper@intel.com
parent d8905ba7

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+3 −4
Original line number Diff line number Diff line
@@ -279,7 +279,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) 
	if (mode & EMIT_INVALIDATE)

		aux_inv = rq->engine->mask & ~BIT(BCS0);

	if (aux_inv)

		cmd += 2 * hweight8(aux_inv) + 2;

		cmd += 2 * hweight32(aux_inv) + 2;



	cs = intel_ring_begin(rq, cmd);

	if (IS_ERR(cs))
@@ -313,9 +313,8 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) 
		struct intel_engine_cs *engine;

		unsigned int tmp;



		*cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv));

		for_each_engine_masked(engine, rq->engine->gt,

				       aux_inv, tmp) {

		*cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv));

		for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) {

			*cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));

			*cs++ = AUX_INV;

		}

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+44 −0
Original line number Diff line number Diff line
@@ -101,6 +101,34 @@ static const struct engine_info intel_engines[] = { 
			{ .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }

		},

	},

	[VCS4] = {

		.class = VIDEO_DECODE_CLASS,

		.instance = 4,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE }

		},

	},

	[VCS5] = {

		.class = VIDEO_DECODE_CLASS,

		.instance = 5,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE }

		},

	},

	[VCS6] = {

		.class = VIDEO_DECODE_CLASS,

		.instance = 6,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE }

		},

	},

	[VCS7] = {

		.class = VIDEO_DECODE_CLASS,

		.instance = 7,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE }

		},

	},

	[VECS0] = {

		.gen6_hw_id = VECS0_HW,

		.class = VIDEO_ENHANCEMENT_CLASS,
@@ -117,6 +145,20 @@ static const struct engine_info intel_engines[] = { 
			{ .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }

		},

	},

	[VECS2] = {

		.class = VIDEO_ENHANCEMENT_CLASS,

		.instance = 2,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE }

		},

	},

	[VECS3] = {

		.class = VIDEO_ENHANCEMENT_CLASS,

		.instance = 3,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }

		},

	},

};



/**
@@ -265,6 +307,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) 


	BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));

	BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));

	BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1));

	BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1));



	if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))

		return -EINVAL;

drivers/gpu/drm/i915/gt/intel_engine_types.h

+10 −4
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ 
#define COPY_ENGINE_CLASS	3

#define OTHER_CLASS		4

#define MAX_ENGINE_CLASS	4

#define MAX_ENGINE_INSTANCE	3

#define MAX_ENGINE_INSTANCE	7



#define I915_MAX_SLICES	3

#define I915_MAX_SUBSLICES 8
@@ -60,7 +60,7 @@ struct intel_gt; 
struct intel_ring;

struct intel_uncore;



typedef u8 intel_engine_mask_t;

typedef u32 intel_engine_mask_t;

#define ALL_ENGINES ((intel_engine_mask_t)~0ul)



struct intel_hw_status_page {
@@ -97,8 +97,8 @@ struct i915_ctx_workarounds { 
	struct i915_vma *vma;

};



#define I915_MAX_VCS	4

#define I915_MAX_VECS	2

#define I915_MAX_VCS	8

#define I915_MAX_VECS	4



/*

 * Engine IDs definitions.
@@ -111,9 +111,15 @@ enum intel_engine_id { 
	VCS1,

	VCS2,

	VCS3,

	VCS4,

	VCS5,

	VCS6,

	VCS7,

#define _VCS(n) (VCS0 + (n))

	VECS0,

	VECS1,

	VECS2,

	VECS3,

#define _VECS(n) (VECS0 + (n))

	I915_NUM_ENGINES

#define INVALID_ENGINE ((enum intel_engine_id)-1)

drivers/gpu/drm/i915/gt/intel_gt_types.h

+3 −2
Original line number Diff line number Diff line
@@ -174,13 +174,14 @@ struct intel_gt { 


	struct intel_gt_info {

		intel_engine_mask_t engine_mask;



		u32 l3bank_mask;



		u8 num_engines;



		/* Media engine access to SFC per instance */

		u8 vdbox_sfc_access;



		u32 l3bank_mask;



		/* Slice/subslice/EU info */

		struct sseu_dev_info sseu;

	} info;

drivers/gpu/drm/i915/i915_pci.c

+3 −2
Original line number Diff line number Diff line
@@ -1001,8 +1001,9 @@ static const struct intel_device_info xehpsdv_info = { 
	.pipe_mask = 0,

	.platform_engine_mask =

		BIT(RCS0) | BIT(BCS0) |

		BIT(VECS0) | BIT(VECS1) |

		BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3),

		BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |

		BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |

		BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7),

	.require_force_probe = 1,

};