Commit 937d6eef authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'docs-5.5a' of git://git.lwn.net/linux 

Pull Documentation updates from Jonathan Corbet:
 "Here are the main documentation changes for 5.5:

   - Various kerneldoc script enhancements.

   - More RST conversions; those are slowing down as we run out of
     things to convert, but we're a ways from done still.

   - Dan's "maintainer profile entry" work landed at last. Now we just
     need to get maintainers to fill in the profiles...

   - A reworking of the parallel build setup to work better with a
     variety of systems (and to not take over huge systems entirely in
     particular).

   - The MAINTAINERS file is now converted to RST during the build.
     Hopefully nobody ever tries to print this thing, or they will need
     to load a lot of paper.

   - A script and documentation making it easy for maintainers to add
     Link: tags at commit time.

  Also included is the removal of a bunch of spurious CR characters"

* tag 'docs-5.5a' of git://git.lwn.net/linux: (91 commits)
  docs: remove a bunch of stray CRs
  docs: fix up the maintainer profile document
  libnvdimm, MAINTAINERS: Maintainer Entry Profile
  Maintainer Handbook: Maintainer Entry Profile
  MAINTAINERS: Reclaim the P: tag for Maintainer Entry Profile
  docs, parallelism: Rearrange how jobserver reservations are made
  docs, parallelism: Do not leak blocking mode to other readers
  docs, parallelism: Fix failure path and add comment
  Documentation: Remove bootmem_debug from kernel-parameters.txt
  Documentation: security: core.rst: fix warnings
  Documentation/process/howto/kokr: Update for 4.x -> 5.x versioning
  Documentation/translation: Use Korean for Korean translation title
  docs/memory-barriers.txt: Remove remaining references to mmiowb()
  docs/memory-barriers.txt/kokr: Update I/O section to be clearer about CPU vs thread
  docs/memory-barriers.txt/kokr: Fix style, spacing and grammar in I/O section
  Documentation/kokr: Kill all references to mmiowb()
  docs/memory-barriers.txt/kokr: Rewrite "KERNEL I/O BARRIER EFFECTS" section
  docs: Add initial documentation for devfreq
  Documentation: Document how to get links with git am
  docs: Add request_irq() documentation
  ...
parents 2c97b5ae 36bb9778

.mailmap

+1 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ Mark Brown <broonie@sirena.org.uk> 
Mark Yao <markyao0591@gmail.com> <mark.yao@rock-chips.com>

Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>

Martin Kepplinger <martink@posteo.de> <martin.kepplinger@ginzinger.com>

Martin Kepplinger <martink@posteo.de> <martin.kepplinger@puri.sm>

Mathieu Othacehe <m.othacehe@gmail.com>

Matthew Wilcox <willy@infradead.org> <matthew.r.wilcox@intel.com>

Matthew Wilcox <willy@infradead.org> <matthew@wil.cx>

CREDITS

+2 −1
Original line number Diff line number Diff line
@@ -1875,8 +1875,9 @@ S: The Netherlands 


N: Martin Kepplinger

E: martink@posteo.de

E: martin.kepplinger@ginzinger.com

E: martin.kepplinger@puri.sm

W: http://www.martinkepplinger.com

P: 4096R/5AB387D3 F208 2B88 0F9E 4239 3468  6E3F 5003 98DF 5AB3 87D3

D: mma8452 accelerators iio driver

D: pegasus_notetaker input driver

D: Kernel fixes and cleanups

Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x

+115 −68
Original line number Diff line number Diff line 
What:		/sys/bus/coresight/devices/<memory_map>.etm/enable_source

What:		/sys/bus/coresight/devices/etm<N>/enable_source

Date:		April 2015

KernelVersion:  4.01

Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
@@ -8,82 +8,82 @@ Description: (RW) Enable/disable tracing on this specific trace entiry. 
		of coresight components linking the source to the sink is

		configured and managed automatically by the coresight framework.



What:		/sys/bus/coresight/devices/<memory_map>.etm/cpu

What:		/sys/bus/coresight/devices/etm<N>/cpu

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) The CPU this tracing entity is associated with.



What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp

What:		/sys/bus/coresight/devices/etm<N>/nr_pe_cmp

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Indicates the number of PE comparator inputs that are

		available for tracing.



What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp

What:		/sys/bus/coresight/devices/etm<N>/nr_addr_cmp

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Indicates the number of address comparator pairs that are

		available for tracing.



What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_cntr

What:		/sys/bus/coresight/devices/etm<N>/nr_cntr

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Indicates the number of counters that are available for

		tracing.



What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp

What:		/sys/bus/coresight/devices/etm<N>/nr_ext_inp

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Indicates how many external inputs are implemented.



What:		/sys/bus/coresight/devices/<memory_map>.etm/numcidc

What:		/sys/bus/coresight/devices/etm<N>/numcidc

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Indicates the number of Context ID comparators that are

		available for tracing.



What:		/sys/bus/coresight/devices/<memory_map>.etm/numvmidc

What:		/sys/bus/coresight/devices/etm<N>/numvmidc

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Indicates the number of VMID comparators that are available

		for tracing.



What:		/sys/bus/coresight/devices/<memory_map>.etm/nrseqstate

What:		/sys/bus/coresight/devices/etm<N>/nrseqstate

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Indicates the number of sequencer states that are

		implemented.



What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_resource

What:		/sys/bus/coresight/devices/etm<N>/nr_resource

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Indicates the number of resource selection pairs that are

		available for tracing.



What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp

What:		/sys/bus/coresight/devices/etm<N>/nr_ss_cmp

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Indicates the number of single-shot comparator controls that

		are available for tracing.



What:		/sys/bus/coresight/devices/<memory_map>.etm/reset

What:		/sys/bus/coresight/devices/etm<N>/reset

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(W) Cancels all configuration on a trace unit and set it back

		to its boot configuration.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mode

What:		/sys/bus/coresight/devices/etm<N>/mode

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
@@ -91,302 +91,349 @@ Description: (RW) Controls various modes supported by this ETM, for example 
		P0 instruction tracing, branch broadcast, cycle counting and

		context ID tracing.



What:		/sys/bus/coresight/devices/<memory_map>.etm/pe

What:		/sys/bus/coresight/devices/etm<N>/pe

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Controls which PE to trace.



What:		/sys/bus/coresight/devices/<memory_map>.etm/event

What:		/sys/bus/coresight/devices/etm<N>/event

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Controls the tracing of arbitrary events from bank 0 to 3.



What:		/sys/bus/coresight/devices/<memory_map>.etm/event_instren

What:		/sys/bus/coresight/devices/etm<N>/event_instren

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Controls the behavior of the events in bank 0 to 3.



What:		/sys/bus/coresight/devices/<memory_map>.etm/event_ts

What:		/sys/bus/coresight/devices/etm<N>/event_ts

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Controls the insertion of global timestamps in the trace

		streams.



What:		/sys/bus/coresight/devices/<memory_map>.etm/syncfreq

What:		/sys/bus/coresight/devices/etm<N>/syncfreq

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Controls how often trace synchronization requests occur.



What:		/sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold

What:		/sys/bus/coresight/devices/etm<N>/cyc_threshold

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Sets the threshold value for cycle counting.



What:		/sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl

What:		/sys/bus/coresight/devices/etm<N>/bb_ctrl

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Controls which regions in the memory map are enabled to

		use branch broadcasting.



What:		/sys/bus/coresight/devices/<memory_map>.etm/event_vinst

What:		/sys/bus/coresight/devices/etm<N>/event_vinst

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Controls instruction trace filtering.



What:		/sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst

What:		/sys/bus/coresight/devices/etm<N>/s_exlevel_vinst

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) In Secure state, each bit controls whether instruction

		tracing is enabled for the corresponding exception level.



What:		/sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst

What:		/sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) In non-secure state, each bit controls whether instruction

		tracing is enabled for the corresponding exception level.



What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_idx

What:		/sys/bus/coresight/devices/etm<N>/addr_idx

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Select which address comparator or pair (of comparators) to

		work with.



What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype

What:		/sys/bus/coresight/devices/etm<N>/addr_instdatatype

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Controls what type of comparison the trace unit performs.



What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_single

What:		/sys/bus/coresight/devices/etm<N>/addr_single

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Used to setup single address comparator values.



What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_range

What:		/sys/bus/coresight/devices/etm<N>/addr_range

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Used to setup address range comparator values.



What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_idx

What:		/sys/bus/coresight/devices/etm<N>/seq_idx

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Select which sequensor.



What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_state

What:		/sys/bus/coresight/devices/etm<N>/seq_state

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Use this to set, or read, the sequencer state.



What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_event

What:		/sys/bus/coresight/devices/etm<N>/seq_event

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Moves the sequencer state to a specific state.



What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event

What:		/sys/bus/coresight/devices/etm<N>/seq_reset_event

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Moves the sequencer to state 0 when a programmed event

		occurs.



What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_idx

What:		/sys/bus/coresight/devices/etm<N>/cntr_idx

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Select which counter unit to work with.



What:		/sys/bus/coresight/devices/<memory_map>.etm/cntrldvr

What:		/sys/bus/coresight/devices/etm<N>/cntrldvr

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) This sets or returns the reload count value of the

		specific counter.



What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_val

What:		/sys/bus/coresight/devices/etm<N>/cntr_val

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) This sets or returns the current count value of the

                specific counter.



What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl

What:		/sys/bus/coresight/devices/etm<N>/cntr_ctrl

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Controls the operation of the selected counter.



What:		/sys/bus/coresight/devices/<memory_map>.etm/res_idx

What:		/sys/bus/coresight/devices/etm<N>/res_idx

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Select which resource selection unit to work with.



What:		/sys/bus/coresight/devices/<memory_map>.etm/res_ctrl

What:		/sys/bus/coresight/devices/etm<N>/res_ctrl

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description: 	(RW) Controls the selection of the resources in the trace unit.



What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx

What:		/sys/bus/coresight/devices/etm<N>/ctxid_idx

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Select which context ID comparator to work with.



What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid

What:		/sys/bus/coresight/devices/etm<N>/ctxid_pid

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Get/Set the context ID comparator value to trigger on.



What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks

What:		/sys/bus/coresight/devices/etm<N>/ctxid_masks

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Mask for all 8 context ID comparator value

		registers (if implemented).



What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_idx

What:		/sys/bus/coresight/devices/etm<N>/vmid_idx

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Select which virtual machine ID comparator to work with.



What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_val

What:		/sys/bus/coresight/devices/etm<N>/vmid_val

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Get/Set the virtual machine ID comparator value to

		trigger on.



What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_masks

What:		/sys/bus/coresight/devices/etm<N>/vmid_masks

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Mask for all 8 virtual machine ID comparator value

		registers (if implemented).



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr

What:		/sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns

Date:		December 2019

KernelVersion:	5.5

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Set the Exception Level matching bits for secure and

		non-secure exception levels.



What:		/sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop

Date:		December 2019

KernelVersion:	5.5

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Access the start stop control register for PE input

		comparators.



What:		/sys/bus/coresight/devices/etm<N>/addr_cmp_view

Date:		December 2019

KernelVersion:	5.5

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the current settings for the selected address

		comparator.



What:		/sys/bus/coresight/devices/etm<N>/sshot_idx

Date:		December 2019

KernelVersion:	5.5

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Select the single shot control register to access.



What:		/sys/bus/coresight/devices/etm<N>/sshot_ctrl

Date:		December 2019

KernelVersion:	5.5

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Access the selected single shot control register.



What:		/sys/bus/coresight/devices/etm<N>/sshot_status

Date:		December 2019

KernelVersion:	5.5

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the current value of the selected single shot

		status register.



What:		/sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl

Date:		December 2019

KernelVersion:	5.5

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(RW) Access the selected single show PE comparator control

		register.



What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the OS Lock Status Register (0x304).

		The value it taken directly  from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr

What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the Power Down Control Register

		(0x310).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr

What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the Power Down Status Register

		(0x314).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr

What:		/sys/bus/coresight/devices/etm<N>/mgmt/trclsr

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the SW Lock Status Register

		(0xFB4).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus

What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the Authentication Status Register

		(0xFB8).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid

What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevid

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the Device ID Register

		(0xFC8).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype

What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the Device Type Register

		(0xFCC).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0

What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the Peripheral ID0 Register

		(0xFE0).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1

What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the Peripheral ID1 Register

		(0xFE4).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2

What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the Peripheral ID2 Register

		(0xFE8).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3

What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the Peripheral ID3 Register

		(0xFEC).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig

What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcconfig

Date:		February 2016

KernelVersion:	4.07

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the trace configuration register

		(0x010) as currently set by SW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid

What:		/sys/bus/coresight/devices/etm<N>/mgmt/trctraceid

Date:		February 2016

KernelVersion:	4.07

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Print the content of the trace ID register (0x040).



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0

What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr0

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Returns the tracing capabilities of the trace unit (0x1E0).

		The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1

What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr1

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Returns the tracing capabilities of the trace unit (0x1E4).

		The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2

What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr2

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
@@ -394,7 +441,7 @@ Description: (R) Returns the maximum size of the data value, data address, 
		VMID, context ID and instuction address in the trace unit

		(0x1E8).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3

What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr3

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
@@ -403,42 +450,42 @@ Description: (R) Returns the value associated with various resources 
		architecture specification for more details (0x1E8).

		The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4

What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr4

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Returns how many resources the trace unit supports (0x1F0).

		The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5

What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr5

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Returns how many resources the trace unit supports (0x1F4).

		The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8

What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr8

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Returns the maximum speculation depth of the instruction

		trace stream. (0x180).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9

What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr9

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Returns the number of P0 right-hand keys that the trace unit

		can use (0x184).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10

What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr10

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(R) Returns the number of P1 right-hand keys that the trace unit

		can use (0x188).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11

What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr11

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
@@ -446,7 +493,7 @@ Description: (R) Returns the number of special P1 right-hand keys that the 
		trace unit can use (0x18C).  The value is taken directly from

		the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12

What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr12

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
@@ -454,7 +501,7 @@ Description: (R) Returns the number of conditional P1 right-hand keys that 
		the trace unit can use (0x190).  The value is taken directly

		from the HW.



What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13

What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr13

Date:		April 2015

KernelVersion:	4.01

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Documentation/Makefile

+3 −3
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ endif 
SPHINXBUILD   = sphinx-build

SPHINXOPTS    =

SPHINXDIRS    = .

_SPHINXDIRS   = $(patsubst $(srctree)/Documentation/%/conf.py,%,$(wildcard $(srctree)/Documentation/*/conf.py))

_SPHINXDIRS   = $(patsubst $(srctree)/Documentation/%/index.rst,%,$(wildcard $(srctree)/Documentation/*/index.rst))

SPHINX_CONF   = conf.py

PAPER         =

BUILDDIR      = $(obj)/output
@@ -33,8 +33,6 @@ ifeq ($(HAVE_SPHINX),0) 


else # HAVE_SPHINX



export SPHINXOPTS = $(shell perl -e 'open IN,"sphinx-build --version 2>&1 |"; while (<IN>) { if (m/([\d\.]+)/) { print "-jauto" if ($$1 >= "1.7") } ;} close IN')



# User-friendly check for pdflatex and latexmk

HAVE_PDFLATEX := $(shell if which $(PDFLATEX) >/dev/null 2>&1; then echo 1; else echo 0; fi)

HAVE_LATEXMK := $(shell if which latexmk >/dev/null 2>&1; then echo 1; else echo 0; fi)
@@ -67,6 +65,8 @@ quiet_cmd_sphinx = SPHINX $@ --> file://$(abspath $(BUILDDIR)/$3/$4) 
      cmd_sphinx = $(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=Documentation/media $2 && \

	PYTHONDONTWRITEBYTECODE=1 \

	BUILDDIR=$(abspath $(BUILDDIR)) SPHINX_CONF=$(abspath $(srctree)/$(src)/$5/$(SPHINX_CONF)) \

	$(PYTHON) $(srctree)/scripts/jobserver-exec \

	$(SHELL) $(srctree)/Documentation/sphinx/parallel-wrapper.sh \

	$(SPHINXBUILD) \

	-b $2 \

	-c $(abspath $(srctree)/$(src)) \

Documentation/admin-guide/LSM/SafeSetID.rst

+2 −2

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