Commit 93235bfd authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge tag 'amd-drm-fixes-6.2-2023-01-04' of... 

Merge tag 'amd-drm-fixes-6.2-2023-01-04' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.2-2023-01-04:

amdgpu:
- DCN 3.2 fix
- Display fix

amdkfd:
- Fix kernel warning

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230105033839.23711-1-alexander.deucher@amd.com
parents 83e79ae3 6fe6ece3

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -195,6 +195,7 @@ extern int amdgpu_emu_mode; 
extern uint amdgpu_smu_memory_pool_size;

extern int amdgpu_smu_pptable_id;

extern uint amdgpu_dc_feature_mask;

extern uint amdgpu_freesync_vid_mode;

extern uint amdgpu_dc_debug_mask;

extern uint amdgpu_dc_visual_confirm;

extern uint amdgpu_dm_abm_level;

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+27 −0
Original line number Diff line number Diff line
@@ -181,6 +181,7 @@ int amdgpu_mes_kiq; 
int amdgpu_noretry = -1;

int amdgpu_force_asic_type = -1;

int amdgpu_tmz = -1; /* auto */

uint amdgpu_freesync_vid_mode;

int amdgpu_reset_method = -1; /* auto */

int amdgpu_num_kcq = -1;

int amdgpu_smartshift_bias;
@@ -879,6 +880,32 @@ module_param_named(backlight, amdgpu_backlight, bint, 0444); 
MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");

module_param_named(tmz, amdgpu_tmz, int, 0444);



/**

 * DOC: freesync_video (uint)

 * Enable the optimization to adjust front porch timing to achieve seamless

 * mode change experience when setting a freesync supported mode for which full

 * modeset is not needed.

 *

 * The Display Core will add a set of modes derived from the base FreeSync

 * video mode into the corresponding connector's mode list based on commonly

 * used refresh rates and VRR range of the connected display, when users enable

 * this feature. From the userspace perspective, they can see a seamless mode

 * change experience when the change between different refresh rates under the

 * same resolution. Additionally, userspace applications such as Video playback

 * can read this modeset list and change the refresh rate based on the video

 * frame rate. Finally, the userspace can also derive an appropriate mode for a

 * particular refresh rate based on the FreeSync Mode and add it to the

 * connector's mode list.

 *

 * Note: This is an experimental feature.

 *

 * The default value: 0 (off).

 */

MODULE_PARM_DESC(

	freesync_video,

	"Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");

module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);



/**

 * DOC: reset_method (int)

 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

+1 −1
Original line number Diff line number Diff line
@@ -801,7 +801,7 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, 


		p2plink->attr.name = "properties";

		p2plink->attr.mode = KFD_SYSFS_FILE_MODE;

		sysfs_attr_init(&iolink->attr);

		sysfs_attr_init(&p2plink->attr);

		ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);

		if (ret < 0)

			return ret;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+7 −5
Original line number Diff line number Diff line
@@ -5835,7 +5835,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 
		 */

		DRM_DEBUG_DRIVER("No preferred mode found\n");

	} else {

		recalculate_timing = is_freesync_video_mode(&mode, aconnector);

		recalculate_timing = amdgpu_freesync_vid_mode &&

				 is_freesync_video_mode(&mode, aconnector);

		if (recalculate_timing) {

			freesync_mode = get_highest_refresh_rate_mode(aconnector, false);

			drm_mode_copy(&saved_mode, &mode);
@@ -6986,7 +6987,7 @@ static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connect 
	struct amdgpu_dm_connector *amdgpu_dm_connector =

		to_amdgpu_dm_connector(connector);



	if (!edid)

	if (!(amdgpu_freesync_vid_mode && edid))

		return;



	if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
@@ -8850,7 +8851,8 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 
		 * TODO: Refactor this function to allow this check to work

		 * in all conditions.

		 */

		if (dm_new_crtc_state->stream &&

		if (amdgpu_freesync_vid_mode &&

		    dm_new_crtc_state->stream &&

		    is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))

			goto skip_modeset;
@@ -8885,7 +8887,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 
		if (!dm_old_crtc_state->stream)

			goto skip_modeset;



		if (dm_new_crtc_state->stream &&

		if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&

		    is_timing_unchanged_for_freesync(new_crtc_state,

						     old_crtc_state)) {

			new_crtc_state->mode_changed = false;
@@ -8897,7 +8899,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 
			set_freesync_fixed_config(dm_new_crtc_state);



			goto skip_modeset;

		} else if (aconnector &&

		} else if (amdgpu_freesync_vid_mode && aconnector &&

			   is_freesync_video_mode(&new_crtc_state->mode,

						  aconnector)) {

			struct drm_display_mode *high_mode;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

+3 −3
Original line number Diff line number Diff line
@@ -6259,10 +6259,10 @@ bool dml32_CalculateDETSwathFillLatencyHiding(unsigned int NumberOfActiveSurface 


	/* calculate sum of single swath size for all pipes in bytes */

	for (k = 0; k < NumberOfActiveSurfaces; k++) {

		SwathSizePerSurfaceY[k] += SwathHeightY[k] * SwathWidthY[k] * BytePerPixelInDETY[k] * NumOfDPP[k];

		SwathSizePerSurfaceY[k] = SwathHeightY[k] * SwathWidthY[k] * BytePerPixelInDETY[k] * NumOfDPP[k];



		if (SwathHeightC[k] != 0)

			SwathSizePerSurfaceC[k] += SwathHeightC[k] * SwathWidthC[k] * BytePerPixelInDETC[k] * NumOfDPP[k];

			SwathSizePerSurfaceC[k] = SwathHeightC[k] * SwathWidthC[k] * BytePerPixelInDETC[k] * NumOfDPP[k];

		else

			SwathSizePerSurfaceC[k] = 0;