Commit 93134b0a authored by Vidya Sagar's avatar Vidya Sagar Committed by Vinod Koul
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dt-bindings: PHY: P2U: Add support for Tegra234 P2U block



Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue
module instantiated once for each PCIe lane between Synopsys DesignWare
core based PCIe IP and Universal PHY block.

Signed-off-by: default avatarVidya Sagar <vidyas@nvidia.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220629060435.25297-2-vidyas@nvidia.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent e4e46bc7
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+13 −4
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@
$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: NVIDIA Tegra194 P2U binding
title: NVIDIA Tegra194 & Tegra234 P2U binding

maintainers:
  - Thierry Reding <treding@nvidia.com>
@@ -12,13 +12,17 @@ maintainers:
description: >
  Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
  Speed) each interfacing with 12 and 8 P2U instances respectively.
  Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
  each interfacing with 8, 8 and 8 P2U instances respectively.
  A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
  interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
  lane.
  interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
  PCIe lane.

properties:
  compatible:
    const: nvidia,tegra194-p2u
    enum:
      - nvidia,tegra194-p2u
      - nvidia,tegra234-p2u

  reg:
    maxItems: 1
@@ -28,6 +32,11 @@ properties:
    items:
      - const: ctl

  nvidia,skip-sz-protect-en:
    description: Should be present if two PCIe retimers are present between
      the root port and its immediate downstream device.
    type: boolean

  '#phy-cells':
    const: 0