Merge tag 'br-v5.18r' of git://linuxtv.org/hverkuil/media_tree into media_stage (92ec1a5c) · Commits · EulixOS / Software / Kernel

Documentation/devicetree/bindings/media/amphion,vpu.yaml

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		# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Amphion VPU codec IP

		maintainers:
		- Ming Qian <ming.qian@nxp.com>
		- Shijie Qin <shijie.qin@nxp.com>

		description: \|-
		The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present
		on NXP i.MX8Q SoCs.

		properties:
		$nodename:
		pattern: "^vpu@[0-9a-f]+$"

		compatible:
		items:
		- enum:
		- nxp,imx8qm-vpu
		- nxp,imx8qxp-vpu

		reg:
		maxItems: 1

		power-domains:
		maxItems: 1

		"#address-cells":
		const: 1

		"#size-cells":
		const: 1

		ranges: true

		patternProperties:
		"^mailbox@[0-9a-f]+$":
		description:
		Each vpu encoder or decoder correspond a MU, which used for communication
		between driver and firmware. Implement via mailbox on driver.
		$ref: ../mailbox/fsl,mu.yaml#


		"^vpu_core@[0-9a-f]+$":
		description:
		Each core correspond a decoder or encoder, need to configure them
		separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
		has one decoder and one encoder.
		type: object

		properties:
		compatible:
		items:
		- enum:
		- nxp,imx8q-vpu-decoder
		- nxp,imx8q-vpu-encoder

		reg:
		maxItems: 1

		power-domains:
		maxItems: 1

		mbox-names:
		items:
		- const: tx0
		- const: tx1
		- const: rx

		mboxes:
		description:
		List of phandle of 2 MU channels for tx, 1 MU channel for rx.
		maxItems: 3

		memory-region:
		description:
		Phandle to the reserved memory nodes to be associated with the
		remoteproc device. The reserved memory nodes should be carveout nodes,
		and should be defined as per the bindings in
		Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
		items:
		- description: region reserved for firmware image sections.
		- description: region used for RPC shared memory between firmware and
		driver.

		required:
		- compatible
		- reg
		- power-domains
		- mbox-names
		- mboxes
		- memory-region

		additionalProperties: false

		required:
		- compatible
		- reg
		- power-domains

		additionalProperties: false

		examples:
		# Device node example for i.MX8QM platform:
		- \|
		#include <dt-bindings/firmware/imx/rsrc.h>

		vpu: vpu@2c000000 {
		compatible = "nxp,imx8qm-vpu";
		ranges = <0x2c000000 0x2c000000 0x2000000>;
		reg = <0x2c000000 0x1000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&pd IMX_SC_R_VPU>;

		mu_m0: mailbox@2d000000 {
		compatible = "fsl,imx6sx-mu";
		reg = <0x2d000000 0x20000>;
		interrupts = <0 472 4>;
		#mbox-cells = <2>;
		power-domains = <&pd IMX_SC_R_VPU_MU_0>;
		};

		mu1_m0: mailbox@2d020000 {
		compatible = "fsl,imx6sx-mu";
		reg = <0x2d020000 0x20000>;
		interrupts = <0 473 4>;
		#mbox-cells = <2>;
		power-domains = <&pd IMX_SC_R_VPU_MU_1>;
		};

		mu2_m0: mailbox@2d040000 {
		compatible = "fsl,imx6sx-mu";
		reg = <0x2d040000 0x20000>;
		interrupts = <0 474 4>;
		#mbox-cells = <2>;
		power-domains = <&pd IMX_SC_R_VPU_MU_2>;
		};

		vpu_core0: vpu_core@2d080000 {
		compatible = "nxp,imx8q-vpu-decoder";
		reg = <0x2d080000 0x10000>;
		power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
		mbox-names = "tx0", "tx1", "rx";
		mboxes = <&mu_m0 0 0>,
		<&mu_m0 0 1>,
		<&mu_m0 1 0>;
		memory-region = <&decoder_boot>, <&decoder_rpc>;
		};

		vpu_core1: vpu_core@2d090000 {
		compatible = "nxp,imx8q-vpu-encoder";
		reg = <0x2d090000 0x10000>;
		power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
		mbox-names = "tx0", "tx1", "rx";
		mboxes = <&mu1_m0 0 0>,
		<&mu1_m0 0 1>,
		<&mu1_m0 1 0>;
		memory-region = <&encoder1_boot>, <&encoder1_rpc>;
		};

		vpu_core2: vpu_core@2d0a0000 {
		reg = <0x2d0a0000 0x10000>;
		compatible = "nxp,imx8q-vpu-encoder";
		power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
		mbox-names = "tx0", "tx1", "rx";
		mboxes = <&mu2_m0 0 0>,
		<&mu2_m0 0 1>,
		<&mu2_m0 1 0>;
		memory-region = <&encoder2_boot>, <&encoder2_rpc>;
		};
		};

		...

Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst

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		@@ -257,6 +257,8 @@ of the luma plane.
		.. _V4L2-PIX-FMT-NV12-4L4:
		.. _V4L2-PIX-FMT-NV12-16L16:
		.. _V4L2-PIX-FMT-NV12-32L32:
		.. _V4L2_PIX_FMT_NV12M_8L128:
		.. _V4L2_PIX_FMT_NV12M_10BE_8L128:

		Tiled NV12
		----------
		@@ -281,21 +283,41 @@ If the vertical resolution is an odd number of tiles, the last row of
		tiles is stored in linear order. The layouts of the luma and chroma
		planes are identical.

		``V4L2_PIX_FMT_NV12_4L4`` stores pixel in 4x4 tiles, and stores
		``V4L2_PIX_FMT_NV12_4L4`` stores pixels in 4x4 tiles, and stores
		tiles linearly in memory. The line stride and image height must be
		aligned to a multiple of 4. The layouts of the luma and chroma planes are
		identical.

		``V4L2_PIX_FMT_NV12_16L16`` stores pixel in 16x16 tiles, and stores
		``V4L2_PIX_FMT_NV12_16L16`` stores pixels in 16x16 tiles, and stores
		tiles linearly in memory. The line stride and image height must be
		aligned to a multiple of 16. The layouts of the luma and chroma planes are
		identical.

		``V4L2_PIX_FMT_NV12_32L32`` stores pixel in 32x32 tiles, and stores
		``V4L2_PIX_FMT_NV12_32L32`` stores pixels in 32x32 tiles, and stores
		tiles linearly in memory. The line stride and image height must be
		aligned to a multiple of 32. The layouts of the luma and chroma planes are
		identical.

		``V4L2_PIX_FMT_NV12M_8L128`` is similar to ``V4L2_PIX_FMT_NV12M`` but stores
		pixels in 2D 8x128 tiles, and stores tiles linearly in memory.
		The image height must be aligned to a multiple of 128.
		The layouts of the luma and chroma planes are identical.

		``V4L2_PIX_FMT_NV12M_10BE_8L128`` is similar to ``V4L2_PIX_FMT_NV12M`` but stores
		10 bits pixels in 2D 8x128 tiles, and stores tiles linearly in memory.
		the data is arranged in big endian order.
		The image height must be aligned to a multiple of 128.
		The layouts of the luma and chroma planes are identical.
		Note the tile size is 8bytes multiplied by 128 bytes,
		it means that the low bits and high bits of one pixel may be in different tiles.
		The 10 bit pixels are packed, so 5 bytes contain 4 10-bit pixels layout like
		this (for luma):
		byte 0: Y0(bits 9-2)
		byte 1: Y0(bits 1-0) Y1(bits 9-4)
		byte 2: Y1(bits 3-0) Y2(bits 9-6)
		byte 3: Y2(bits 5-0) Y3(bits 9-8)
		byte 4: Y3(bits 7-0)

		``V4L2_PIX_FMT_MM21`` store luma pixel in 16x32 tiles, and chroma pixels
		in 16x16 tiles. The line stride must be aligned to a multiple of 16 and the
		image height must be aligned to a multiple of 32. The number of luma and chroma

MAINTAINERS

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		@@ -1030,6 +1030,15 @@ S: Maintained
		F: Documentation/hid/amd-sfh*
		F: drivers/hid/amd-sfh-hid/

		AMPHION VPU CODEC V4L2 DRIVER
		M: Ming Qian <ming.qian@nxp.com>
		M: Shijie Qin <shijie.qin@nxp.com>
		M: Zhou Peng <eagle.zhou@nxp.com>
		L: linux-media@vger.kernel.org
		S: Maintained
		F: Documentation/devicetree/bindings/media/amphion,vpu.yaml
		F: drivers/media/platform/amphion/

		AMS AS73211 DRIVER
		M: Christian Eggers <ceggers@arri.de>
		L: linux-iio@vger.kernel.org

drivers/media/platform/Kconfig

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		@@ -648,6 +648,25 @@ config VIDEO_TEGRA_VDE
		Support for the NVIDIA Tegra video decoder unit.
		To compile this driver as a module choose m here.

		config VIDEO_AMPHION_VPU
		tristate "Amphion VPU (Video Processing Unit) Codec IP"
		depends on ARCH_MXC \|\| COMPILE_TEST
		depends on MEDIA_SUPPORT
		depends on VIDEO_DEV
		depends on VIDEO_V4L2
		select MEDIA_CONTROLLER
		select V4L2_MEM2MEM_DEV
		select VIDEOBUF2_DMA_CONTIG
		select VIDEOBUF2_VMALLOC
		help
		Amphion VPU Codec IP contains two parts: Windsor and Malone.
		Windsor is encoder that supports H.264, and Malone is decoder
		that supports H.264, HEVC, and other video formats.
		This is a V4L2 driver for NXP MXC 8Q video accelerator hardware.
		It accelerates encoding and decoding operations on
		various NXP SoCs.
		To compile this driver as a module choose m here.

		endif # V4L_MEM2MEM_DRIVERS

		# TI VIDEO PORT Helper Modules

drivers/media/platform/Makefile

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		@@ -92,3 +92,5 @@ obj-y += sunxi/
		obj-$(CONFIG_VIDEO_MESON_GE2D) += meson/ge2d/

		obj-$(CONFIG_VIDEO_TEGRA_VDE) += tegra/vde/

		obj-$(CONFIG_VIDEO_AMPHION_VPU) += amphion/