Unverified Commit 92e55a86 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge tag 'dt-fixes-for-palmer-6.0-rc3' of... 

Merge tag 'dt-fixes-for-palmer-6.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git

 into fixes

Microchip RISC-V devicetree fixes for 6.0-rc3

Two sets of fixes this time around:
- A fix for the interrupt ordering of the l2-cache controller. If the
  driver is enabled, it would spam the console /constantly/, rendering
  the system useless.
- General cleanup for some bogus properties in the dt, part of my quest
  for zero dtbs_check warnings.

On that note, the interrupt ordering adds a dtbs_check warning - but I
considered that fixing the potentially useless system was more of a
priority.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>

* tag 'dt-fixes-for-palmer-6.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git:
  riscv: dts: microchip: mpfs: remove pci axi address translation property
  riscv: dts: microchip: mpfs: remove bogus card-detect-delay
  riscv: dts: microchip: mpfs: remove ti,fifo-depth property
  riscv: dts: microchip: mpfs: fix incorrect pcie child node name
  riscv: dts: microchip: correct L2 cache interrupts
parents 96264230 e4009c5f

arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts

+0 −3
Original line number Diff line number Diff line
@@ -84,12 +84,10 @@ 


	phy1: ethernet-phy@9 {

		reg = <9>;

		ti,fifo-depth = <0x1>;

	};



	phy0: ethernet-phy@8 {

		reg = <8>;

		ti,fifo-depth = <0x1>;

	};

};
@@ -102,7 +100,6 @@ 
	disable-wp;

	cap-sd-highspeed;

	cap-mmc-highspeed;

	card-detect-delay = <200>;

	mmc-ddr-1_8v;

	mmc-hs200-1_8v;

	sd-uhs-sdr12;

arch/riscv/boot/dts/microchip/mpfs-polarberry.dts

+0 −3
Original line number Diff line number Diff line
@@ -54,12 +54,10 @@ 


	phy1: ethernet-phy@5 {

		reg = <5>;

		ti,fifo-depth = <0x01>;

	};



	phy0: ethernet-phy@4 {

		reg = <4>;

		ti,fifo-depth = <0x01>;

	};

};
@@ -72,7 +70,6 @@ 
	disable-wp;

	cap-sd-highspeed;

	cap-mmc-highspeed;

	card-detect-delay = <200>;

	mmc-ddr-1_8v;

	mmc-hs200-1_8v;

	sd-uhs-sdr12;

arch/riscv/boot/dts/microchip/mpfs.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -193,7 +193,7 @@ 
			cache-size = <2097152>;

			cache-unified;

			interrupt-parent = <&plic>;

			interrupts = <1>, <2>, <3>;

			interrupts = <1>, <3>, <4>, <2>;

		};



		clint: clint@2000000 {
@@ -485,9 +485,8 @@ 
			ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;

			msi-parent = <&pcie>;

			msi-controller;

			microchip,axi-m-atr0 = <0x10 0x0>;

			status = "disabled";

			pcie_intc: legacy-interrupt-controller {

			pcie_intc: interrupt-controller {

				#address-cells = <0>;

				#interrupt-cells = <1>;

				interrupt-controller;