Commit 92e11ddb authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-display-for-6.2' of https://gitlab.freedesktop.org/lumag/msm into drm-next 



drm/msm updates for 6.2

Core:
- MSM_INFO_GET_FLAGS support
- Cleaned up MSM IOMMU wrapper code

DPU:
- Added support for XR30 and P010 image formats
- Reworked MDSS/DPU schema, added SM8250 MDSS bindings
- Added Qualcomm SM6115 support

DP:
- Dropped unsane sanity checks

DSI:
- Fix calculation of DSC pps payload

DSI PHY:
- DSI PHY support for QCM2290

HDMI:
- Reworked dev init path

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20221126102141.721353-1-dmitry.baryshkov@linaro.org
parents f513a19a 8d1d17d4

Documentation/devicetree/bindings/display/msm/dpu-common.yaml

0 → 100644
+52 −0
Original line number Diff line number Diff line 
%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/dpu-common.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display DPU common properties



maintainers:

  - Krishna Manikandan <quic_mkrishn@quicinc.com>

  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

  - Rob Clark <robdclark@gmail.com>



description: |

  Common properties for QCom DPU display controller.



properties:

  interrupts:

    maxItems: 1



  power-domains:

    maxItems: 1



  operating-points-v2: true

  opp-table:

    type: object



  ports:

    $ref: /schemas/graph.yaml#/properties/ports

    description: |

      Contains the list of output ports from DPU device. These ports

      connect to interfaces that are external to the DPU hardware,

      such as DSI, DP etc.



    patternProperties:

      "^port@[0-9a-f]+$":

        $ref: /schemas/graph.yaml#/properties/port



    # at least one port is required

    required:

      - port@0



required:

  - compatible

  - reg

  - reg-names

  - clocks

  - interrupts

  - power-domains

  - operating-points-v2

  - ports



additionalProperties: true

Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml

deleted100644 → 0
+0 −235
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display DPU dt properties for SC7180 target



maintainers:

  - Krishna Manikandan <quic_mkrishn@quicinc.com>



description: |

  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates

  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree

  bindings of MDSS and DPU are mentioned for SC7180 target.



properties:

  compatible:

    items:

      - const: qcom,sc7180-mdss



  reg:

    maxItems: 1



  reg-names:

    const: mdss



  power-domains:

    maxItems: 1



  clocks:

    items:

      - description: Display AHB clock from gcc

      - description: Display AHB clock from dispcc

      - description: Display core clock



  clock-names:

    items:

      - const: iface

      - const: ahb

      - const: core



  interrupts:

    maxItems: 1



  interrupt-controller: true



  "#address-cells": true



  "#size-cells": true



  "#interrupt-cells":

    const: 1



  iommus:

    items:

      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0



  ranges: true



  interconnects:

    items:

      - description: Interconnect path specifying the port ids for data bus



  interconnect-names:

    const: mdp0-mem



  resets:

    items:

      - description: MDSS_CORE reset



patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    description: Node containing the properties of DPU.

    additionalProperties: false



    properties:

      compatible:

        items:

          - const: qcom,sc7180-dpu



      reg:

        items:

          - description: Address offset and size for mdp register set

          - description: Address offset and size for vbif register set



      reg-names:

        items:

          - const: mdp

          - const: vbif



      clocks:

        items:

          - description: Display hf axi clock

          - description: Display ahb clock

          - description: Display rotator clock

          - description: Display lut clock

          - description: Display core clock

          - description: Display vsync clock



      clock-names:

        items:

          - const: bus

          - const: iface

          - const: rot

          - const: lut

          - const: core

          - const: vsync



      interrupts:

        maxItems: 1



      power-domains:

        maxItems: 1



      operating-points-v2: true

      opp-table:

        type: object



      ports:

        $ref: /schemas/graph.yaml#/properties/ports

        description: |

          Contains the list of output ports from DPU device. These ports

          connect to interfaces that are external to the DPU hardware,

          such as DSI, DP etc. Each output port contains an endpoint that

          describes how it is connected to an external interface.



        properties:

          port@0:

            $ref: /schemas/graph.yaml#/properties/port

            description: DPU_INTF1 (DSI1)



          port@2:

            $ref: /schemas/graph.yaml#/properties/port

            description: DPU_INTF0 (DP)



        required:

          - port@0



    required:

      - compatible

      - reg

      - reg-names

      - clocks

      - interrupts

      - power-domains

      - operating-points-v2

      - ports



required:

  - compatible

  - reg

  - reg-names

  - power-domains

  - clocks

  - interrupts

  - interrupt-controller

  - iommus

  - ranges



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>

    #include <dt-bindings/clock/qcom,gcc-sc7180.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interconnect/qcom,sdm845.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    display-subsystem@ae00000 {

         #address-cells = <1>;

         #size-cells = <1>;

         compatible = "qcom,sc7180-mdss";

         reg = <0xae00000 0x1000>;

         reg-names = "mdss";

         power-domains = <&dispcc MDSS_GDSC>;

         clocks = <&gcc GCC_DISP_AHB_CLK>,

                  <&dispcc DISP_CC_MDSS_AHB_CLK>,

                  <&dispcc DISP_CC_MDSS_MDP_CLK>;

         clock-names = "iface", "ahb", "core";



         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

         interrupt-controller;

         #interrupt-cells = <1>;



         interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;

         interconnect-names = "mdp0-mem";



         iommus = <&apps_smmu 0x800 0x2>;

         ranges;



         display-controller@ae01000 {

                   compatible = "qcom,sc7180-dpu";

                   reg = <0x0ae01000 0x8f000>,

                         <0x0aeb0000 0x2008>;



                   reg-names = "mdp", "vbif";



                   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

                            <&dispcc DISP_CC_MDSS_AHB_CLK>,

                            <&dispcc DISP_CC_MDSS_ROT_CLK>,

                            <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

                            <&dispcc DISP_CC_MDSS_MDP_CLK>,

                            <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

                   clock-names = "bus", "iface", "rot", "lut", "core",

                                 "vsync";



                   interrupt-parent = <&mdss>;

                   interrupts = <0>;

                   power-domains = <&rpmhpd SC7180_CX>;

                   operating-points-v2 = <&mdp_opp_table>;



                   ports {

                           #address-cells = <1>;

                           #size-cells = <0>;



                           port@0 {

                                   reg = <0>;

                                   dpu_intf1_out: endpoint {

                                                  remote-endpoint = <&dsi0_in>;

                                   };

                           };



                            port@2 {

                                    reg = <2>;

                                    dpu_intf0_out: endpoint {

                                                   remote-endpoint = <&dp_in>;

                                    };

                            };

                   };

         };

    };

...

Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml

deleted100644 → 0
+0 −239
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display DPU dt properties for SC7280



maintainers:

  - Krishna Manikandan <quic_mkrishn@quicinc.com>



description: |

  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates

  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree

  bindings of MDSS and DPU are mentioned for SC7280.



properties:

  compatible:

    const: qcom,sc7280-mdss



  reg:

    maxItems: 1



  reg-names:

    const: mdss



  power-domains:

    maxItems: 1



  clocks:

    items:

      - description: Display AHB clock from gcc

      - description: Display AHB clock from dispcc

      - description: Display core clock



  clock-names:

    items:

      - const: iface

      - const: ahb

      - const: core



  interrupts:

    maxItems: 1



  interrupt-controller: true



  "#address-cells": true



  "#size-cells": true



  "#interrupt-cells":

    const: 1



  iommus:

    items:

      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0



  ranges: true



  interconnects:

    items:

      - description: Interconnect path specifying the port ids for data bus



  interconnect-names:

    const: mdp0-mem



  resets:

    items:

      - description: MDSS_CORE reset



patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    description: Node containing the properties of DPU.

    additionalProperties: false



    properties:

      compatible:

        const: qcom,sc7280-dpu



      reg:

        items:

          - description: Address offset and size for mdp register set

          - description: Address offset and size for vbif register set



      reg-names:

        items:

          - const: mdp

          - const: vbif



      clocks:

        items:

          - description: Display hf axi clock

          - description: Display sf axi clock

          - description: Display ahb clock

          - description: Display lut clock

          - description: Display core clock

          - description: Display vsync clock



      clock-names:

        items:

          - const: bus

          - const: nrt_bus

          - const: iface

          - const: lut

          - const: core

          - const: vsync



      interrupts:

        maxItems: 1



      power-domains:

        maxItems: 1



      operating-points-v2: true

      opp-table:

        type: object



      ports:

        $ref: /schemas/graph.yaml#/properties/ports

        description: |

          Contains the list of output ports from DPU device. These ports

          connect to interfaces that are external to the DPU hardware,

          such as DSI, DP etc. Each output port contains an endpoint that

          describes how it is connected to an external interface.



        properties:

          port@0:

            $ref: /schemas/graph.yaml#/properties/port

            description: DPU_INTF1 (DSI)



          port@1:

            $ref: /schemas/graph.yaml#/properties/port

            description: DPU_INTF5 (EDP)



        required:

          - port@0



    required:

      - compatible

      - reg

      - reg-names

      - clocks

      - interrupts

      - power-domains

      - operating-points-v2

      - ports



required:

  - compatible

  - reg

  - reg-names

  - power-domains

  - clocks

  - interrupts

  - interrupt-controller

  - iommus

  - ranges



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,dispcc-sc7280.h>

    #include <dt-bindings/clock/qcom,gcc-sc7280.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interconnect/qcom,sc7280.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    display-subsystem@ae00000 {

         #address-cells = <1>;

         #size-cells = <1>;

         compatible = "qcom,sc7280-mdss";

         reg = <0xae00000 0x1000>;

         reg-names = "mdss";

         power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;

         clocks = <&gcc GCC_DISP_AHB_CLK>,

                  <&dispcc DISP_CC_MDSS_AHB_CLK>,

                  <&dispcc DISP_CC_MDSS_MDP_CLK>;

         clock-names = "iface",

                       "ahb",

                       "core";



         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

         interrupt-controller;

         #interrupt-cells = <1>;



         interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;

         interconnect-names = "mdp0-mem";



         iommus = <&apps_smmu 0x900 0x402>;

         ranges;



         display-controller@ae01000 {

                   compatible = "qcom,sc7280-dpu";

                   reg = <0x0ae01000 0x8f000>,

                         <0x0aeb0000 0x2008>;



                   reg-names = "mdp", "vbif";



                   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

                            <&gcc GCC_DISP_SF_AXI_CLK>,

                            <&dispcc DISP_CC_MDSS_AHB_CLK>,

                            <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

                            <&dispcc DISP_CC_MDSS_MDP_CLK>,

                            <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

                   clock-names = "bus",

                                 "nrt_bus",

                                 "iface",

                                 "lut",

                                 "core",

                                 "vsync";



                   interrupt-parent = <&mdss>;

                   interrupts = <0>;

                   power-domains = <&rpmhpd SC7280_CX>;

                   operating-points-v2 = <&mdp_opp_table>;



                   ports {

                           #address-cells = <1>;

                           #size-cells = <0>;



                           port@0 {

                                   reg = <0>;

                                   dpu_intf1_out: endpoint {

                                           remote-endpoint = <&dsi0_in>;

                                   };

                           };



                           port@1 {

                                   reg = <1>;

                                   dpu_intf5_out: endpoint {

                                           remote-endpoint = <&edp_in>;

                                   };

                           };

                   };

         };

    };

...

Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml

deleted100644 → 0
+0 −217
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display DPU dt properties for SDM845 target



maintainers:

  - Krishna Manikandan <quic_mkrishn@quicinc.com>



description: |

  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates

  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree

  bindings of MDSS and DPU are mentioned for SDM845 target.



properties:

  compatible:

    items:

      - const: qcom,sdm845-mdss



  reg:

    maxItems: 1



  reg-names:

    const: mdss



  power-domains:

    maxItems: 1



  clocks:

    items:

      - description: Display AHB clock from gcc

      - description: Display core clock



  clock-names:

    items:

      - const: iface

      - const: core



  interrupts:

    maxItems: 1



  interrupt-controller: true



  "#address-cells": true



  "#size-cells": true



  "#interrupt-cells":

    const: 1



  iommus:

    items:

      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0

      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1



  ranges: true



  resets:

    items:

      - description: MDSS_CORE reset



patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    description: Node containing the properties of DPU.

    additionalProperties: false



    properties:

      compatible:

        items:

          - const: qcom,sdm845-dpu



      reg:

        items:

          - description: Address offset and size for mdp register set

          - description: Address offset and size for vbif register set



      reg-names:

        items:

          - const: mdp

          - const: vbif



      clocks:

        items:

          - description: Display ahb clock

          - description: Display axi clock

          - description: Display core clock

          - description: Display vsync clock



      clock-names:

        items:

          - const: iface

          - const: bus

          - const: core

          - const: vsync



      interrupts:

        maxItems: 1



      power-domains:

        maxItems: 1



      operating-points-v2: true

      opp-table:

        type: object



      ports:

        $ref: /schemas/graph.yaml#/properties/ports

        description: |

          Contains the list of output ports from DPU device. These ports

          connect to interfaces that are external to the DPU hardware,

          such as DSI, DP etc. Each output port contains an endpoint that

          describes how it is connected to an external interface.



        properties:

          port@0:

            $ref: /schemas/graph.yaml#/properties/port

            description: DPU_INTF1 (DSI1)



          port@1:

            $ref: /schemas/graph.yaml#/properties/port

            description: DPU_INTF2 (DSI2)



        required:

          - port@0

          - port@1



    required:

      - compatible

      - reg

      - reg-names

      - clocks

      - interrupts

      - power-domains

      - operating-points-v2

      - ports



required:

  - compatible

  - reg

  - reg-names

  - power-domains

  - clocks

  - interrupts

  - interrupt-controller

  - iommus

  - ranges



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>

    #include <dt-bindings/clock/qcom,gcc-sdm845.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    display-subsystem@ae00000 {

          #address-cells = <1>;

          #size-cells = <1>;

          compatible = "qcom,sdm845-mdss";

          reg = <0x0ae00000 0x1000>;

          reg-names = "mdss";

          power-domains = <&dispcc MDSS_GDSC>;



          clocks = <&gcc GCC_DISP_AHB_CLK>,

                   <&dispcc DISP_CC_MDSS_MDP_CLK>;

          clock-names = "iface", "core";



          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

          interrupt-controller;

          #interrupt-cells = <1>;



          iommus = <&apps_smmu 0x880 0x8>,

                   <&apps_smmu 0xc80 0x8>;

          ranges;



          display-controller@ae01000 {

                    compatible = "qcom,sdm845-dpu";

                    reg = <0x0ae01000 0x8f000>,

                          <0x0aeb0000 0x2008>;

                    reg-names = "mdp", "vbif";



                    clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

                             <&dispcc DISP_CC_MDSS_AXI_CLK>,

                             <&dispcc DISP_CC_MDSS_MDP_CLK>,

                             <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

                    clock-names = "iface", "bus", "core", "vsync";



                    interrupt-parent = <&mdss>;

                    interrupts = <0>;

                    power-domains = <&rpmhpd SDM845_CX>;

                    operating-points-v2 = <&mdp_opp_table>;



                    ports {

                           #address-cells = <1>;

                           #size-cells = <0>;



                           port@0 {

                                   reg = <0>;

                                   dpu_intf1_out: endpoint {

                                                  remote-endpoint = <&dsi0_in>;

                                   };

                           };



                           port@1 {

                                   reg = <1>;

                                   dpu_intf2_out: endpoint {

                                                  remote-endpoint = <&dsi1_in>;

                                   };

                           };

                    };

          };

    };

...

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

+4 −1
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ properties: 
    maxItems: 1



  phy-names:

    deprecated: true

    const: dsi



  "#address-cells": true
@@ -80,6 +81,9 @@ properties: 


  operating-points-v2: true



  opp-table:

    type: object



  ports:

    $ref: "/schemas/graph.yaml#/properties/ports"

    description: |
@@ -131,7 +135,6 @@ required: 
  - clocks

  - clock-names

  - phys

  - phy-names

  - assigned-clocks

  - assigned-clock-parents

  - power-domains