Commit 92ceebf9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mailbox-v5.20' of git://git.linaro.org/landing-teams/working/fujitsu/integration 

Pull mailbox updates from Jassi Brar:

 - mtk:
     - use rx_callback instead of cmdq_task_cb

 - qcom:
     - add syscon const
     - add SM6375 compatible

 - imx:
     - enable RST channel
     - clear pending irqs

* tag 'mailbox-v5.20' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: imx: clear pending interrupts
  dt-bindings: mailbox: qcom-ipcc: Add SM6375 compatible
  mailbox: imx: support RST channel
  dt-bindings: mailbox: imx-mu: add RST channel
  dt-bindings: mailbox: qcom,apcs-kpss-global: Add syscon const for relevant entries
  mailbox: mtk-cmdq: Remove proprietary cmdq_task_cb
parents df7a456e 8a8dc2b9

Documentation/devicetree/bindings/mailbox/fsl,mu.yaml

+4 −2
Original line number Diff line number Diff line
@@ -72,14 +72,16 @@ properties: 
      type      : Channel type

      channel   : Channel number



      This MU support 4 type of unidirectional channels, each type

      has 4 channels. A total of 16 channels. Following types are

      This MU support 5 type of unidirectional channels, each type

      has 4 channels except RST channel which only has 1 channel.

      A total of 17 channels.  Following types are

      supported:

      0 - TX channel with 32bit transmit register and IRQ transmit

          acknowledgment support.

      1 - RX channel with 32bit receive register and IRQ support

      2 - TX doorbell channel. Without own register and no ACK support.

      3 - RX doorbell channel.

      4 - RST channel

    const: 2



  clocks:

Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml

+25 −21
Original line number Diff line number Diff line
@@ -15,18 +15,15 @@ maintainers: 


properties:

  compatible:

    enum:

    oneOf:

      - items:

          - enum:

              - qcom,ipq6018-apcs-apps-global

              - qcom,ipq8074-apcs-apps-global

      - qcom,msm8916-apcs-kpss-global

      - qcom,msm8939-apcs-kpss-global

      - qcom,msm8953-apcs-kpss-global

              - qcom,msm8976-apcs-kpss-global

      - qcom,msm8994-apcs-kpss-global

              - qcom,msm8996-apcs-hmss-global

              - qcom,msm8998-apcs-hmss-global

              - qcom,qcm2290-apcs-hmss-global

      - qcom,qcs404-apcs-apps-global

              - qcom,sc7180-apss-shared

              - qcom,sc8180x-apss-shared

              - qcom,sdm660-apcs-hmss-global
@@ -34,7 +31,14 @@ properties: 
              - qcom,sm6125-apcs-hmss-global

              - qcom,sm6115-apcs-hmss-global

              - qcom,sm8150-apss-shared



      - items:

          - enum:

              - qcom,msm8916-apcs-kpss-global

              - qcom,msm8939-apcs-kpss-global

              - qcom,msm8953-apcs-kpss-global

              - qcom,msm8994-apcs-kpss-global

              - qcom,qcs404-apcs-apps-global

          - const: syscon

  reg:

    maxItems: 1
@@ -121,7 +125,7 @@ examples: 
    #define GCC_APSS_AHB_CLK_SRC  1

    #define GCC_GPLL0_AO_OUT_MAIN 123

    apcs: mailbox@b011000 {

        compatible = "qcom,qcs404-apcs-apps-global";

        compatible = "qcom,qcs404-apcs-apps-global", "syscon";

        reg = <0x0b011000 0x1000>;

        #mbox-cells = <1>;

        clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;

Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ properties: 
    items:

      - enum:

          - qcom,sm6350-ipcc

          - qcom,sm6375-ipcc

          - qcom,sm8250-ipcc

          - qcom,sm8350-ipcc

          - qcom,sm8450-ipcc

drivers/mailbox/imx-mailbox.c

+34 −6
Original line number Diff line number Diff line
@@ -19,13 +19,15 @@ 
#include <linux/suspend.h>

#include <linux/slab.h>



#define IMX_MU_CHANS		16

#define IMX_MU_CHANS		17

/* TX0/RX0/RXDB[0-3] */

#define IMX_MU_SCU_CHANS	6

/* TX0/RX0 */

#define IMX_MU_S4_CHANS		2

#define IMX_MU_CHAN_NAME_SIZE	20



#define IMX_MU_NUM_RR		4



#define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))

#define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))
@@ -35,9 +37,11 @@ enum imx_mu_chan_type { 
	IMX_MU_TYPE_RX		= 1, /* Rx */

	IMX_MU_TYPE_TXDB	= 2, /* Tx doorbell */

	IMX_MU_TYPE_RXDB	= 3, /* Rx doorbell */

	IMX_MU_TYPE_RST		= 4, /* Reset */

};



enum imx_mu_xcr {

	IMX_MU_CR,

	IMX_MU_GIER,

	IMX_MU_GCR,

	IMX_MU_TCR,
@@ -50,6 +54,7 @@ enum imx_mu_xsr { 
	IMX_MU_GSR,

	IMX_MU_TSR,

	IMX_MU_RSR,

	IMX_MU_xSR_MAX,

};



struct imx_sc_rpc_msg_max {
@@ -85,7 +90,7 @@ struct imx_mu_priv { 
	int			irq[IMX_MU_CHANS];

	bool			suspend;



	u32 xcr[4];

	u32 xcr[IMX_MU_xCR_MAX];



	bool			side_b;

};
@@ -105,8 +110,8 @@ struct imx_mu_dcfg { 
	enum imx_mu_type type;

	u32	xTR;		/* Transmit Register0 */

	u32	xRR;		/* Receive Register0 */

	u32	xSR[4];		/* Status Registers */

	u32	xCR[4];		/* Control Registers */

	u32	xSR[IMX_MU_xSR_MAX];	/* Status Registers */

	u32	xCR[IMX_MU_xCR_MAX];	/* Control Registers */

};



#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
@@ -121,6 +126,9 @@ struct imx_mu_dcfg { 
#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))

/* General Purpose Interrupt Request */

#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))

/* MU reset */

#define IMX_MU_xCR_RST(type)	(type & IMX_MU_V2 ? BIT(0) : BIT(5))

#define IMX_MU_xSR_RST(type)	(type & IMX_MU_V2 ? BIT(0) : BIT(7))





static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
@@ -497,6 +505,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p) 
		val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &

			(ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));

		break;

	case IMX_MU_TYPE_RST:

		return IRQ_NONE;

	default:

		dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",

				     cp->type);
@@ -581,6 +591,8 @@ static void imx_mu_shutdown(struct mbox_chan *chan) 
{

	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);

	struct imx_mu_con_priv *cp = chan->con_priv;

	int ret;

	u32 sr;



	if (cp->type == IMX_MU_TYPE_TXDB) {

		tasklet_kill(&cp->txdb_tasklet);
@@ -598,6 +610,13 @@ static void imx_mu_shutdown(struct mbox_chan *chan) 
	case IMX_MU_TYPE_RXDB:

		imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));

		break;

	case IMX_MU_TYPE_RST:

		imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);

		ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr,

					 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5);

		if (ret)

			dev_warn(priv->dev, "RST channel timeout\n");

		break;

	default:

		break;

	}
@@ -694,6 +713,7 @@ static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox, 
static void imx_mu_init_generic(struct imx_mu_priv *priv)

{

	unsigned int i;

	unsigned int val;



	for (i = 0; i < IMX_MU_CHANS; i++) {

		struct imx_mu_con_priv *cp = &priv->con_priv[i];
@@ -715,6 +735,14 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv) 
	/* Set default MU configuration */

	for (i = 0; i < IMX_MU_xCR_MAX; i++)

		imx_mu_write(priv, 0, priv->dcfg->xCR[i]);



	/* Clear any pending GIP */

	val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);

	imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);



	/* Clear any pending RSR */

	for (i = 0; i < IMX_MU_NUM_RR; i++)

		imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);

}



static void imx_mu_init_specific(struct imx_mu_priv *priv)
@@ -865,7 +893,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { 
	.xTR	= 0x0,

	.xRR	= 0x10,

	.xSR	= {0x20, 0x20, 0x20, 0x20},

	.xCR	= {0x24, 0x24, 0x24, 0x24},

	.xCR	= {0x24, 0x24, 0x24, 0x24, 0x24},

};



static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
@@ -888,7 +916,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { 
	.xTR	= 0x200,

	.xRR	= 0x280,

	.xSR	= {0xC, 0x118, 0x124, 0x12C},

	.xCR	= {0x110, 0x114, 0x120, 0x128},

	.xCR	= {0x8, 0x110, 0x114, 0x120, 0x128},

};



static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {

drivers/mailbox/mtk-cmdq-mailbox.c

+0 −11
Original line number Diff line number Diff line
@@ -192,15 +192,10 @@ static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread) 


static void cmdq_task_exec_done(struct cmdq_task *task, int sta)

{

	struct cmdq_task_cb *cb = &task->pkt->async_cb;

	struct cmdq_cb_data data;



	data.sta = sta;

	data.data = cb->data;

	data.pkt = task->pkt;

	if (cb->cb)

		cb->cb(data);



	mbox_chan_received_data(task->thread->chan, &data);



	list_del(&task->list_entry);
@@ -448,7 +443,6 @@ static void cmdq_mbox_shutdown(struct mbox_chan *chan) 
static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout)

{

	struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;

	struct cmdq_task_cb *cb;

	struct cmdq_cb_data data;

	struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);

	struct cmdq_task *task, *tmp;
@@ -465,13 +459,8 @@ static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout) 


	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,

				 list_entry) {

		cb = &task->pkt->async_cb;

		data.sta = -ECONNABORTED;

		data.data = cb->data;

		data.pkt = task->pkt;

		if (cb->cb)

			cb->cb(data);



		mbox_chan_received_data(task->thread->chan, &data);

		list_del(&task->list_entry);

		kfree(task);