Commit 92cbbadf authored by H. Peter Anvin (Intel)'s avatar H. Peter Anvin (Intel) Committed by Ingo Molnar
Browse files

x86/gsseg: Use the LKGS instruction if available for load_gs_index() 



The LKGS instruction atomically loads a segment descriptor into the
%gs descriptor registers, *except* that %gs.base is unchanged, and the
base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly
what we want this function to do.

Signed-off-by: default avatarH. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: default avatarXin Li <xin3.li@intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Acked-by: default avatarPeter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20230112072032.35626-6-xin3.li@intel.com
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
parent ae53fa18

arch/x86/include/asm/gsseg.h

+29 −4
Original line number Diff line number Diff line
@@ -14,17 +14,42 @@ 


extern asmlinkage void asm_load_gs_index(u16 selector);



/* Replace with "lkgs %di" once binutils support LKGS instruction */

#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7)



static inline void native_lkgs(unsigned int selector)

{

	u16 sel = selector;

	asm_inline volatile("1: " LKGS_DI

			    _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel])

			    : [sel] "+D" (sel));

}



static inline void native_load_gs_index(unsigned int selector)

{

	if (cpu_feature_enabled(X86_FEATURE_LKGS)) {

		native_lkgs(selector);

	} else {

		unsigned long flags;



		local_irq_save(flags);

		asm_load_gs_index(selector);

		local_irq_restore(flags);

	}

}



#endif /* CONFIG_X86_64 */



static inline void __init lkgs_init(void)

{

#ifdef CONFIG_PARAVIRT_XXL

#ifdef CONFIG_X86_64

	if (cpu_feature_enabled(X86_FEATURE_LKGS))

		pv_ops.cpu.load_gs_index = native_lkgs;

#endif

#endif

}



#ifndef CONFIG_PARAVIRT_XXL



static inline void load_gs_index(unsigned int selector)

arch/x86/kernel/cpu/common.c

+1 −0
Original line number Diff line number Diff line
@@ -1960,6 +1960,7 @@ void __init identify_boot_cpu(void) 
	setup_cr_pinning();



	tsx_init();

	lkgs_init();

}



void identify_secondary_cpu(struct cpuinfo_x86 *c)

arch/x86/xen/enlighten_pv.c

+1 −0
Original line number Diff line number Diff line
@@ -276,6 +276,7 @@ static void __init xen_init_capabilities(void) 
	setup_clear_cpu_cap(X86_FEATURE_ACC);

	setup_clear_cpu_cap(X86_FEATURE_X2APIC);

	setup_clear_cpu_cap(X86_FEATURE_SME);

	setup_clear_cpu_cap(X86_FEATURE_LKGS);



	/*

	 * Xen PV would need some work to support PCID: CR3 handling as well