Unverified Commit 92a66cbf authored by Mika Westerberg's avatar Mika Westerberg Committed by Mark Brown
Browse files

spi: intel: Use correct mask for flash and protected regions 



The flash and protected region mask is actually 0x7fff (30:16 and 14:0)
and not 0x3fff so fix this accordingly. While there use GENMASK() instead.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20221025062800.22357-1-mika.westerberg@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent cf82d0ec

drivers/spi/spi-intel.c

+4 −4
Original line number Diff line number Diff line
@@ -52,17 +52,17 @@ 
#define FRACC				0x50



#define FREG(n)				(0x54 + ((n) * 4))

#define FREG_BASE_MASK			0x3fff

#define FREG_BASE_MASK			GENMASK(14, 0)

#define FREG_LIMIT_SHIFT		16

#define FREG_LIMIT_MASK			(0x03fff << FREG_LIMIT_SHIFT)

#define FREG_LIMIT_MASK			GENMASK(30, 16)



/* Offset is from @ispi->pregs */

#define PR(n)				((n) * 4)

#define PR_WPE				BIT(31)

#define PR_LIMIT_SHIFT			16

#define PR_LIMIT_MASK			(0x3fff << PR_LIMIT_SHIFT)

#define PR_LIMIT_MASK			GENMASK(30, 16)

#define PR_RPE				BIT(15)

#define PR_BASE_MASK			0x3fff

#define PR_BASE_MASK			GENMASK(14, 0)



/* Offsets are from @ispi->sregs */

#define SSFSTS_CTL			0x00