Commit 927a8e38 authored by Dnyaneshwar Bhadane's avatar Dnyaneshwar Bhadane Committed by Radhakrishna Sripada
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drm/i915/hsw: s/HSW/HASWELL for platform/subplatform defines 



Follow consistent naming convention. Replace HSW with
HASWELL.

Signed-off-by: default avatarDnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-2-dnyaneshwar.bhadane@intel.com
parent 2612e3bb

drivers/gpu/drm/i915/display/intel_cdclk.c

+1 −1
Original line number Diff line number Diff line
@@ -470,7 +470,7 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 
		cdclk_config->cdclk = 450000;

	else if (freq == LCPLL_CLK_FREQ_450)

		cdclk_config->cdclk = 450000;

	else if (IS_HSW_ULT(dev_priv))

	else if (IS_HASWELL_ULT(dev_priv))

		cdclk_config->cdclk = 337500;

	else

		cdclk_config->cdclk = 540000;

drivers/gpu/drm/i915/display/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -7377,7 +7377,7 @@ static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 
	if (DISPLAY_VER(dev_priv) >= 9)

		return false;



	if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))

	if (IS_HASWELL_ULT(dev_priv) || IS_BDW_ULT(dev_priv))

		return false;



	if (HAS_PCH_LPT_H(dev_priv) &&

drivers/gpu/drm/i915/display/intel_display_device.h

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ struct drm_printer; 
#define HAS_GMCH(i915)			(DISPLAY_INFO(i915)->has_gmch)

#define HAS_HW_SAGV_WM(i915)		(DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))

#define HAS_IPC(i915)			(DISPLAY_INFO(i915)->has_ipc)

#define HAS_IPS(i915)			(IS_HSW_ULT(i915) || IS_BROADWELL(i915))

#define HAS_IPS(i915)			(IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))

#define HAS_LSPCON(i915)		(IS_DISPLAY_VER(i915, 9, 10))

#define HAS_MBUS_JOINING(i915)		(IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)

#define HAS_MSO(i915)			(DISPLAY_VER(i915) >= 12)

drivers/gpu/drm/i915/display/intel_dp.c

+1 −1
Original line number Diff line number Diff line
@@ -510,7 +510,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) 
	} else if (DISPLAY_VER(dev_priv) == 9) {

		source_rates = skl_rates;

		size = ARRAY_SIZE(skl_rates);

	} else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||

	} else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||

		   IS_BROADWELL(dev_priv)) {

		source_rates = hsw_rates;

		size = ARRAY_SIZE(hsw_rates);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -927,7 +927,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, 
	switch (wrpll & WRPLL_REF_MASK) {

	case WRPLL_REF_SPECIAL_HSW:

		/* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */

		if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {

		if (IS_HASWELL(dev_priv) && !IS_HASWELL_ULT(dev_priv)) {

			refclk = dev_priv->display.dpll.ref_clks.nssc;

			break;

		}