Commit 9270c565 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'octeontx2-traffic-shaping' 



Sunil Goutham says:

====================
Octeontx2: Traffic shaping and SDP link config support

This patch series adds support for traffic shaping configuration
on all silicons available after 96xx C0. And also adds SDP link
related configuration needed when Octeon is connected as an end-point
and traffic needs to flow from end-point to host and vice versa.

Series also has other changes like
- New mbox messages in admin function driver for PF/VF drivers
  to retrieve available HW resource count. HW resources like block LFs,
  bandwidth profiles etc are covered.
- Added PTP device ID for new CN10K and 95O silicons.
- etc
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents fbcf8a34 66c312ea

drivers/net/ethernet/marvell/octeontx2/af/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -10,4 +10,5 @@ obj-$(CONFIG_OCTEONTX2_AF) += rvu_af.o 
rvu_mbox-y := mbox.o rvu_trace.o

rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \

		  rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \

		  rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o
 
		  rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \

		  rvu_sdp.o

drivers/net/ethernet/marvell/octeontx2/af/common.h

+4 −1
Original line number Diff line number Diff line
@@ -185,6 +185,7 @@ enum nix_scheduler { 


#define NIX_INTF_TYPE_CGX		0

#define NIX_INTF_TYPE_LBK		1

#define NIX_INTF_TYPE_SDP		2



#define MAX_LMAC_PKIND			12

#define NIX_LINK_CGX_LMAC(a, b)		(0 + 4 * (a) + (b))
@@ -192,6 +193,8 @@ enum nix_scheduler { 
#define NIX_CHAN_CGX_LMAC_CHX(a, b, c)	(0x800 + 0x100 * (a) + 0x10 * (b) + (c))

#define NIX_CHAN_LBK_CHX(a, b)		(0 + 0x100 * (a) + (b))

#define NIX_CHAN_SDP_CH_START          (0x700ull)

#define NIX_CHAN_SDP_CHX(a)            (NIX_CHAN_SDP_CH_START + (a))

#define NIX_CHAN_SDP_NUM_CHANS		256



/* The mask is to extract lower 10-bits of channel number

 * which CPT will pass to X2P.

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+72 −8
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ struct mbox_msghdr { 
#define OTX2_MBOX_REQ_SIG (0xdead)

#define OTX2_MBOX_RSP_SIG (0xbeef)

	u16 sig;         /* Signature, for validating corrupted msgs */

#define OTX2_MBOX_VERSION (0x0007)

#define OTX2_MBOX_VERSION (0x0009)

	u16 ver;         /* Version of msg's structure for this ID */

	u16 next_msgoff; /* Offset of next msg within mailbox region */

	int rc;          /* Msg process'ed response code */
@@ -130,6 +130,7 @@ static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 
M(READY,		0x001, ready, msg_req, ready_msg_rsp)		\

M(ATTACH_RESOURCES,	0x002, attach_resources, rsrc_attach, msg_rsp)	\

M(DETACH_RESOURCES,	0x003, detach_resources, rsrc_detach, msg_rsp)	\

M(FREE_RSRC_CNT,	0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp)	\

M(MSIX_OFFSET,		0x005, msix_offset, msg_req, msix_offset_rsp)	\

M(VF_FLR,		0x006, vf_flr, msg_req, msg_rsp)		\

M(PTP_OP,		0x007, ptp_op, ptp_req, ptp_rsp)		\
@@ -191,6 +192,9 @@ M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 
M(CPT_STATS,            0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp)	\

M(CPT_RXC_TIME_CFG,     0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req,  \

			       msg_rsp)                                 \

/* SDP mbox IDs (range 0x1000 - 0x11FF) */				\

M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \

M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \

/* NPC mbox IDs (range 0x6000 - 0x7FFF) */				\

M(NPC_MCAM_ALLOC_ENTRY,	0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\

				npc_mcam_alloc_entry_rsp)		\
@@ -243,7 +247,8 @@ M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 
M(NIX_TXSCH_ALLOC,	0x8004, nix_txsch_alloc,			\

				 nix_txsch_alloc_req, nix_txsch_alloc_rsp)   \

M(NIX_TXSCH_FREE,	0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \

M(NIX_TXSCHQ_CFG,	0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp)  \

M(NIX_TXSCHQ_CFG,	0x8006, nix_txschq_cfg, nix_txschq_config,	\

				nix_txschq_config)			\

M(NIX_STATS_RST,	0x8007, nix_stats_rst, msg_req, msg_rsp)	\

M(NIX_VTAG_CFG,		0x8008, nix_vtag_cfg, nix_vtag_config,		\

				 nix_vtag_config_rsp)			\
@@ -274,7 +279,9 @@ M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 
M(NIX_BANDPROF_ALLOC,	0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \

				nix_bandprof_alloc_rsp)			    \

M(NIX_BANDPROF_FREE,	0x801e, nix_bandprof_free, nix_bandprof_free_req,   \

				msg_rsp)

				msg_rsp)				    \

M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req,		\

				nix_bandprof_get_hwinfo_rsp)



/* Messages initiated by AF (range 0xC00 - 0xDFF) */

#define MBOX_UP_CGX_MESSAGES						\
@@ -363,6 +370,25 @@ struct rsrc_detach { 
	u8 cptlfs:1;

};



/* Number of resources available to the caller.

 * In reply to MBOX_MSG_FREE_RSRC_CNT.

 */

struct free_rsrcs_rsp {

	struct mbox_msghdr hdr;

	u16 schq[NIX_TXSCH_LVL_CNT];

	u16  sso;

	u16  tim;

	u16  ssow;

	u16  cpt;

	u8   npa;

	u8   nix;

	u16  schq_nix1[NIX_TXSCH_LVL_CNT];

	u8   nix1;

	u8   cpt1;

	u8   ree0;

	u8   ree1;

};



#define MSIX_VECTOR_INVALID	0xFFFF

#define MAX_RVU_BLKLF_CNT	256
@@ -370,16 +396,20 @@ struct msix_offset_rsp { 
	struct mbox_msghdr hdr;

	u16  npa_msixoff;

	u16  nix_msixoff;

	u8   sso;

	u8   ssow;

	u8   timlfs;

	u8   cptlfs;

	u16  sso;

	u16  ssow;

	u16  timlfs;

	u16  cptlfs;

	u16  sso_msixoff[MAX_RVU_BLKLF_CNT];

	u16  ssow_msixoff[MAX_RVU_BLKLF_CNT];

	u16  timlf_msixoff[MAX_RVU_BLKLF_CNT];

	u16  cptlf_msixoff[MAX_RVU_BLKLF_CNT];

	u8   cpt1_lfs;

	u16  cpt1_lfs;

	u16  ree0_lfs;

	u16  ree1_lfs;

	u16  cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];

	u16  ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];

	u16  ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];

};



struct get_hw_cap_rsp {
@@ -699,6 +729,9 @@ struct nix_lf_alloc_req { 
	u16 sso_func;

	u64 rx_cfg;   /* See NIX_AF_LF(0..127)_RX_CFG */

	u64 way_mask;

#define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)

#define NIX_LF_LBK_BLK_SEL	    BIT_ULL(1)

	u64 flags;

};



struct nix_lf_alloc_rsp {
@@ -718,6 +751,7 @@ struct nix_lf_alloc_rsp { 
	u8	cgx_links;  /* No. of CGX links present in HW */

	u8	lbk_links;  /* No. of LBK links present in HW */

	u8	sdp_links;  /* No. of SDP links present in HW */

	u8	tx_link;    /* Transmit channel link number */

};



struct nix_lf_free_req {
@@ -836,6 +870,7 @@ struct nix_txsch_free_req { 
struct nix_txschq_config {

	struct mbox_msghdr hdr;

	u8 lvl;	/* SMQ/MDQ/TL4/TL3/TL2/TL1 */

	u8 read;

#define TXSCHQ_IDX_SHIFT	16

#define TXSCHQ_IDX_MASK		(BIT_ULL(10) - 1)

#define TXSCHQ_IDX(reg, shift)	(((reg) >> (shift)) & TXSCHQ_IDX_MASK)
@@ -843,6 +878,8 @@ struct nix_txschq_config { 
#define MAX_REGS_PER_MBOX_MSG	20

	u64 reg[MAX_REGS_PER_MBOX_MSG];

	u64 regval[MAX_REGS_PER_MBOX_MSG];

	/* All 0's => overwrite with new value */

	u64 regval_mask[MAX_REGS_PER_MBOX_MSG];

};



struct nix_vtag_config {
@@ -1066,6 +1103,12 @@ struct nix_bandprof_free_req { 
	u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];

};



struct nix_bandprof_get_hwinfo_rsp {

	struct mbox_msghdr hdr;

	u16 prof_count[BAND_PROF_NUM_LAYERS];

	u32 policer_timeunit;

};



/* NPC mbox message structs */



#define NPC_MCAM_ENTRY_INVALID	0xFFFF
@@ -1434,6 +1477,27 @@ struct cpt_rxc_time_cfg_req { 
	u16 active_limit;

};



struct sdp_node_info {

	/* Node to which this PF belons to */

	u8 node_id;

	u8 max_vfs;

	u8 num_pf_rings;

	u8 pf_srn;

#define SDP_MAX_VFS	128

	u8 vf_rings[SDP_MAX_VFS];

};



struct sdp_chan_info_msg {

	struct mbox_msghdr hdr;

	struct sdp_node_info info;

};



struct sdp_get_chan_info_msg {

	struct mbox_msghdr hdr;

	u16 chan_base;

	u16 num_chan;

};



/* CGX mailbox error codes

 * Range 1101 - 1200.

 */

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

+18 −25
Original line number Diff line number Diff line
@@ -19,12 +19,11 @@ 
#define PCI_SUBSYS_DEVID_OCTX2_98xx_PTP		0xB100

#define PCI_SUBSYS_DEVID_OCTX2_96XX_PTP		0xB200

#define PCI_SUBSYS_DEVID_OCTX2_95XX_PTP		0xB300

#define PCI_SUBSYS_DEVID_OCTX2_LOKI_PTP		0xB400

#define PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP	0xB400

#define PCI_SUBSYS_DEVID_OCTX2_95MM_PTP		0xB500

#define PCI_SUBSYS_DEVID_CN10K_A_PTP		0xB900

#define PCI_SUBSYS_DEVID_CNF10K_A_PTP		0xBA00

#define PCI_SUBSYS_DEVID_CNF10K_B_PTP		0xBC00

#define PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP	0xB600

#define PCI_DEVID_OCTEONTX2_RST			0xA085

#define PCI_DEVID_CN10K_PTP			0xA09E



#define PCI_PTP_BAR_NO				0

#define PCI_RST_BAR_NO				0
@@ -39,6 +38,9 @@ 
#define RST_MUL_BITS				GENMASK_ULL(38, 33)

#define CLOCK_BASE_RATE				50000000ULL



static struct ptp *first_ptp_block;

static const struct pci_device_id ptp_id_table[];



static u64 get_clock_rate(void)

{

	u64 cfg, ret = CLOCK_BASE_RATE * 16;
@@ -74,23 +76,14 @@ static u64 get_clock_rate(void) 


struct ptp *ptp_get(void)

{

	struct pci_dev *pdev;

	struct ptp *ptp;

	struct ptp *ptp = first_ptp_block;



	/* If the PTP pci device is found on the system and ptp

	 * driver is bound to it then the PTP pci device is returned

	 * to the caller(rvu driver).

	 */

	pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,

			      PCI_DEVID_OCTEONTX2_PTP, NULL);

	if (!pdev)

	/* Check PTP block is present in hardware */

	if (!pci_dev_present(ptp_id_table))

		return ERR_PTR(-ENODEV);



	ptp = pci_get_drvdata(pdev);

	/* Check driver is bound to PTP block */

	if (!ptp)

		ptp = ERR_PTR(-EPROBE_DEFER);

	if (IS_ERR(ptp))

		pci_dev_put(pdev);



	return ptp;

}
@@ -190,6 +183,8 @@ static int ptp_probe(struct pci_dev *pdev, 
	writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP);



	pci_set_drvdata(pdev, ptp);

	if (!first_ptp_block)

		first_ptp_block = ptp;



	return 0;
@@ -204,6 +199,9 @@ static int ptp_probe(struct pci_dev *pdev, 
	 * `dev->driver_data`.

	 */

	pci_set_drvdata(pdev, ERR_PTR(err));

	if (!first_ptp_block)

		first_ptp_block = ERR_PTR(err);



	return 0;

}
@@ -233,19 +231,14 @@ static const struct pci_device_id ptp_id_table[] = { 
			 PCI_SUBSYS_DEVID_OCTX2_95XX_PTP) },

	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,

			 PCI_VENDOR_ID_CAVIUM,

			 PCI_SUBSYS_DEVID_OCTX2_LOKI_PTP) },

			 PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP) },

	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,

			 PCI_VENDOR_ID_CAVIUM,

			 PCI_SUBSYS_DEVID_OCTX2_95MM_PTP) },

	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,

			 PCI_VENDOR_ID_CAVIUM,

			 PCI_SUBSYS_DEVID_CN10K_A_PTP) },

	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,

			 PCI_VENDOR_ID_CAVIUM,

			 PCI_SUBSYS_DEVID_CNF10K_A_PTP) },

	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,

			 PCI_VENDOR_ID_CAVIUM,

			 PCI_SUBSYS_DEVID_CNF10K_B_PTP) },

			 PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP) },

	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_PTP) },

	{ 0, }

};

drivers/net/ethernet/marvell/octeontx2/af/rvu.c

+110 −3
Original line number Diff line number Diff line
@@ -70,18 +70,21 @@ static void rvu_setup_hw_capabilities(struct rvu *rvu) 
	hw->cap.nix_shaping = true;

	hw->cap.nix_tx_link_bp = true;

	hw->cap.nix_rx_multicast = true;

	hw->cap.nix_shaper_toggle_wait = false;

	hw->rvu = rvu;



	if (is_rvu_96xx_B0(rvu)) {

	if (is_rvu_pre_96xx_C0(rvu)) {

		hw->cap.nix_fixed_txschq_mapping = true;

		hw->cap.nix_txsch_per_cgx_lmac = 4;

		hw->cap.nix_txsch_per_lbk_lmac = 132;

		hw->cap.nix_txsch_per_sdp_lmac = 76;

		hw->cap.nix_shaping = false;

		hw->cap.nix_tx_link_bp = false;

		if (is_rvu_96xx_A0(rvu))

		if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu))

			hw->cap.nix_rx_multicast = false;

	}

	if (!is_rvu_pre_96xx_C0(rvu))

		hw->cap.nix_shaper_toggle_wait = true;



	if (!is_rvu_otx2(rvu))

		hw->cap.per_pf_mbox_regs = true;
@@ -1115,6 +1118,12 @@ static int rvu_setup_hw_resources(struct rvu *rvu) 
		goto nix_err;

	}



	err = rvu_sdp_init(rvu);

	if (err) {

		dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__);

		goto nix_err;

	}



	rvu_program_channels(rvu);



	return 0;
@@ -1367,9 +1376,10 @@ int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 
	int blkaddr = BLKADDR_NIX0, vf;

	struct rvu_pfvf *pf;



	pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);



	/* All CGX mapped PFs are set with assigned NIX block during init */

	if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) {

		pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);

		blkaddr = pf->nix_blkaddr;

	} else if (is_afvf(pcifunc)) {

		vf = pcifunc - 1;
@@ -1382,6 +1392,10 @@ int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 
			blkaddr = BLKADDR_NIX0;

	}



	/* if SDP1 then the blkaddr is NIX1 */

	if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1)

		blkaddr = BLKADDR_NIX1;



	switch (blkaddr) {

	case BLKADDR_NIX1:

		pfvf->nix_blkaddr = BLKADDR_NIX1;
@@ -1782,6 +1796,99 @@ int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 
	return 0;

}



int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req,

				   struct free_rsrcs_rsp *rsp)

{

	struct rvu_hwinfo *hw = rvu->hw;

	struct rvu_block *block;

	struct nix_txsch *txsch;

	struct nix_hw *nix_hw;



	mutex_lock(&rvu->rsrc_lock);



	block = &hw->block[BLKADDR_NPA];

	rsp->npa = rvu_rsrc_free_count(&block->lf);



	block = &hw->block[BLKADDR_NIX0];

	rsp->nix = rvu_rsrc_free_count(&block->lf);



	block = &hw->block[BLKADDR_NIX1];

	rsp->nix1 = rvu_rsrc_free_count(&block->lf);



	block = &hw->block[BLKADDR_SSO];

	rsp->sso = rvu_rsrc_free_count(&block->lf);



	block = &hw->block[BLKADDR_SSOW];

	rsp->ssow = rvu_rsrc_free_count(&block->lf);



	block = &hw->block[BLKADDR_TIM];

	rsp->tim = rvu_rsrc_free_count(&block->lf);



	block = &hw->block[BLKADDR_CPT0];

	rsp->cpt = rvu_rsrc_free_count(&block->lf);



	block = &hw->block[BLKADDR_CPT1];

	rsp->cpt1 = rvu_rsrc_free_count(&block->lf);



	if (rvu->hw->cap.nix_fixed_txschq_mapping) {

		rsp->schq[NIX_TXSCH_LVL_SMQ] = 1;

		rsp->schq[NIX_TXSCH_LVL_TL4] = 1;

		rsp->schq[NIX_TXSCH_LVL_TL3] = 1;

		rsp->schq[NIX_TXSCH_LVL_TL2] = 1;

		/* NIX1 */

		if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))

			goto out;

		rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1;

		rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1;

		rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1;

		rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1;

	} else {

		nix_hw = get_nix_hw(hw, BLKADDR_NIX0);

		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];

		rsp->schq[NIX_TXSCH_LVL_SMQ] =

				rvu_rsrc_free_count(&txsch->schq);



		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4];

		rsp->schq[NIX_TXSCH_LVL_TL4] =

				rvu_rsrc_free_count(&txsch->schq);



		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3];

		rsp->schq[NIX_TXSCH_LVL_TL3] =

				rvu_rsrc_free_count(&txsch->schq);



		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];

		rsp->schq[NIX_TXSCH_LVL_TL2] =

				rvu_rsrc_free_count(&txsch->schq);



		if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))

			goto out;



		nix_hw = get_nix_hw(hw, BLKADDR_NIX1);

		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];

		rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] =

				rvu_rsrc_free_count(&txsch->schq);



		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4];

		rsp->schq_nix1[NIX_TXSCH_LVL_TL4] =

				rvu_rsrc_free_count(&txsch->schq);



		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3];

		rsp->schq_nix1[NIX_TXSCH_LVL_TL3] =

				rvu_rsrc_free_count(&txsch->schq);



		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];

		rsp->schq_nix1[NIX_TXSCH_LVL_TL2] =

				rvu_rsrc_free_count(&txsch->schq);

	}



	rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1;

out:

	rsp->schq[NIX_TXSCH_LVL_TL1] = 1;

	mutex_unlock(&rvu->rsrc_lock);



	return 0;

}



int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req,

			    struct msg_rsp *rsp)

{