Loading drivers/net/ipa/ipa_main.c +53 −26 Original line number Diff line number Diff line Loading @@ -183,6 +183,56 @@ static void ipa_teardown(struct ipa *ipa) gsi_teardown(&ipa->gsi); } static void ipa_hardware_config_bcr(struct ipa *ipa, const struct ipa_data *data) { u32 val; /* IPA v4.5+ has no backward compatibility register */ if (ipa->version >= IPA_VERSION_4_5) return; val = data->backward_compat; iowrite32(val, ipa->reg_virt + IPA_REG_BCR_OFFSET); } static void ipa_hardware_config_tx(struct ipa *ipa) { enum ipa_version version = ipa->version; u32 val; if (version <= IPA_VERSION_4_0 || version >= IPA_VERSION_4_5) return; /* Disable PA mask to allow HOLB drop */ val = ioread32(ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); val &= ~PA_MASK_EN_FMASK; iowrite32(val, ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); } static void ipa_hardware_config_clkon(struct ipa *ipa) { enum ipa_version version = ipa->version; u32 val; if (version < IPA_VERSION_3_1 || version >= IPA_VERSION_4_5) return; /* Implement some hardware workarounds */ if (version >= IPA_VERSION_4_0) { /* Enable open global clocks in the CLKON configuration */ val = GLOBAL_FMASK | GLOBAL_2X_CLK_FMASK; } else if (version == IPA_VERSION_3_1) { val = MISC_FMASK; /* Disable MISC clock gating */ } else { return; } iowrite32(val, ipa->reg_virt + IPA_REG_CLKON_CFG_OFFSET); } /* Configure bus access behavior for IPA components */ static void ipa_hardware_config_comp(struct ipa *ipa) { Loading Loading @@ -382,32 +432,9 @@ static void ipa_hardware_dcd_deconfig(struct ipa *ipa) */ static void ipa_hardware_config(struct ipa *ipa, const struct ipa_data *data) { enum ipa_version version = ipa->version; u32 val; /* IPA v4.5+ has no backward compatibility register */ if (version < IPA_VERSION_4_5) { val = data->backward_compat; iowrite32(val, ipa->reg_virt + IPA_REG_BCR_OFFSET); } /* Implement some hardware workarounds */ if (version >= IPA_VERSION_4_0 && version < IPA_VERSION_4_5) { /* Disable PA mask to allow HOLB drop */ val = ioread32(ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); val &= ~PA_MASK_EN_FMASK; iowrite32(val, ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); /* Enable open global clocks in the CLKON configuration */ val = GLOBAL_FMASK | GLOBAL_2X_CLK_FMASK; } else if (version == IPA_VERSION_3_1) { val = MISC_FMASK; /* Disable MISC clock gating */ } else { val = 0; /* No CLKON configuration needed */ } if (val) iowrite32(val, ipa->reg_virt + IPA_REG_CLKON_CFG_OFFSET); ipa_hardware_config_bcr(ipa, data); ipa_hardware_config_tx(ipa); ipa_hardware_config_clkon(ipa); ipa_hardware_config_comp(ipa); ipa_hardware_config_qsb(ipa, data); ipa_hardware_config_timing(ipa); Loading Loading
drivers/net/ipa/ipa_main.c +53 −26 Original line number Diff line number Diff line Loading @@ -183,6 +183,56 @@ static void ipa_teardown(struct ipa *ipa) gsi_teardown(&ipa->gsi); } static void ipa_hardware_config_bcr(struct ipa *ipa, const struct ipa_data *data) { u32 val; /* IPA v4.5+ has no backward compatibility register */ if (ipa->version >= IPA_VERSION_4_5) return; val = data->backward_compat; iowrite32(val, ipa->reg_virt + IPA_REG_BCR_OFFSET); } static void ipa_hardware_config_tx(struct ipa *ipa) { enum ipa_version version = ipa->version; u32 val; if (version <= IPA_VERSION_4_0 || version >= IPA_VERSION_4_5) return; /* Disable PA mask to allow HOLB drop */ val = ioread32(ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); val &= ~PA_MASK_EN_FMASK; iowrite32(val, ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); } static void ipa_hardware_config_clkon(struct ipa *ipa) { enum ipa_version version = ipa->version; u32 val; if (version < IPA_VERSION_3_1 || version >= IPA_VERSION_4_5) return; /* Implement some hardware workarounds */ if (version >= IPA_VERSION_4_0) { /* Enable open global clocks in the CLKON configuration */ val = GLOBAL_FMASK | GLOBAL_2X_CLK_FMASK; } else if (version == IPA_VERSION_3_1) { val = MISC_FMASK; /* Disable MISC clock gating */ } else { return; } iowrite32(val, ipa->reg_virt + IPA_REG_CLKON_CFG_OFFSET); } /* Configure bus access behavior for IPA components */ static void ipa_hardware_config_comp(struct ipa *ipa) { Loading Loading @@ -382,32 +432,9 @@ static void ipa_hardware_dcd_deconfig(struct ipa *ipa) */ static void ipa_hardware_config(struct ipa *ipa, const struct ipa_data *data) { enum ipa_version version = ipa->version; u32 val; /* IPA v4.5+ has no backward compatibility register */ if (version < IPA_VERSION_4_5) { val = data->backward_compat; iowrite32(val, ipa->reg_virt + IPA_REG_BCR_OFFSET); } /* Implement some hardware workarounds */ if (version >= IPA_VERSION_4_0 && version < IPA_VERSION_4_5) { /* Disable PA mask to allow HOLB drop */ val = ioread32(ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); val &= ~PA_MASK_EN_FMASK; iowrite32(val, ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); /* Enable open global clocks in the CLKON configuration */ val = GLOBAL_FMASK | GLOBAL_2X_CLK_FMASK; } else if (version == IPA_VERSION_3_1) { val = MISC_FMASK; /* Disable MISC clock gating */ } else { val = 0; /* No CLKON configuration needed */ } if (val) iowrite32(val, ipa->reg_virt + IPA_REG_CLKON_CFG_OFFSET); ipa_hardware_config_bcr(ipa, data); ipa_hardware_config_tx(ipa); ipa_hardware_config_clkon(ipa); ipa_hardware_config_comp(ipa); ipa_hardware_config_qsb(ipa, data); ipa_hardware_config_timing(ipa); Loading