Commit 91fa5884 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'i2c/for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux 

Pull i2c updates from Wolfram Sang:
 "I2C has quite some patches for you this time. I hope it is the move to
  per-driver-maintainers which is now showing results. We will see.

  The big news is two new drivers (Nuvoton NPCM and Qualcomm CCI),
  larger refactoring of the Designware, Tegra, and PXA drivers, the
  Cadence driver supports being a slave now, and there is support to
  instanciate SPD eeproms for well-known cases (which will be
  user-visible because the i801 driver supports it), and some
  devm_platform_ioremap_resource() conversions which blow up the
  diffstat.

  Note that I applied the Nuvoton driver quite late, so some minor fixup
  patches arrived during the merge window. I chose to apply them right
  away because they were trivial"

* 'i2c/for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (109 commits)
  i2c: Drop stray comma in MODULE_AUTHOR statements
  i2c: npcm7xx: npcm_i2caddr[] can be static
  MAINTAINERS: npcm7xx: Add maintainer for Nuvoton NPCM BMC
  i2c: npcm7xx: Fix a couple of error codes in probe
  i2c: icy: Fix build with CONFIG_AMIGA_PCMCIA=n
  i2c: npcm7xx: Remove unnecessary parentheses
  i2c: npcm7xx: Add support for slave mode for Nuvoton
  i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver
  dt-bindings: i2c: npcm7xx: add NPCM I2C controller
  i2c: pxa: don't error out if there's no pinctrl
  i2c: add 'single-master' property to generic bindings
  i2c: designware: Add Baikal-T1 System I2C support
  i2c: designware: Move reg-space remapping into a dedicated function
  i2c: designware: Retrieve quirk flags as early as possible
  i2c: designware: Convert driver to using regmap API
  i2c: designware: Discard Cherry Trail model flag
  i2c: designware: Add Baytrail sem config DW I2C platform dependency
  i2c: designware: slave: Set DW I2C core module dependency
  i2c: designware: Use `-y` to build multi-object modules
  dt-bindings: i2c: dw: Add Baikal-T1 SoC I2C controller
  ...
parents ac911b31 d790eeb3

Documentation/devicetree/bindings/i2c/i2c-designware.txt

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* Synopsys DesignWare I2C



Required properties :



 - compatible : should be "snps,designware-i2c"

                or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback

 - reg : Offset and length of the register set for the device

 - interrupts : <IRQ> where IRQ is the interrupt number.

 - clocks : phandles for the clocks, see the description of clock-names below.

   The phandle for the "ic_clk" clock is required. The phandle for the "pclk"

   clock is optional. If a single clock is specified but no clock-name, it is

   the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first.



Recommended properties :



 - clock-frequency : desired I2C bus clock frequency in Hz.



Optional properties :



 - clock-names : Contains the names of the clocks:

    "ic_clk", for the core clock used to generate the external I2C clock.

    "pclk", the interface clock, required for register access.



 - reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold

   time, named ICPU_CFG:TWI_DELAY in the datasheet.



 - i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.

   This option is only supported in hardware blocks version 1.11a or newer and

   on Microsemi SoCs ("mscc,ocelot-i2c" compatible).



 - i2c-scl-falling-time-ns : should contain the SCL falling time in nanoseconds.

   This value which is by default 300ns is used to compute the tLOW period.



 - i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds.

   This value which is by default 300ns is used to compute the tHIGH period.



Examples :



	i2c@f0000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "snps,designware-i2c";

		reg = <0xf0000 0x1000>;

		interrupts = <11>;

		clock-frequency = <400000>;

	};



	i2c@1120000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "snps,designware-i2c";

		reg = <0x1120000 0x1000>;

		interrupt-parent = <&ictl>;

		interrupts = <12 1>;

		clock-frequency = <400000>;

		i2c-sda-hold-time-ns = <300>;

		i2c-sda-falling-time-ns = <300>;

		i2c-scl-falling-time-ns = <300>;

	};



	i2c@1120000 {

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x2000 0x100>;

		clock-frequency = <400000>;

		clocks = <&i2cclk>;

		interrupts = <0>;



		eeprom@64 {

			compatible = "linux,slave-24c02";

			reg = <0x40000064>;

		};

	};

Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt

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Qualcomm Camera Control Interface (CCI) I2C controller



PROPERTIES:



- compatible:

	Usage: required

	Value type: <string>

	Definition: must be one of:

		"qcom,msm8916-cci"

		"qcom,msm8996-cci"

		"qcom,sdm845-cci"



- reg

	Usage: required

	Value type: <prop-encoded-array>

	Definition: base address CCI I2C controller and length of memory

		    mapped region.



- interrupts:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: specifies the CCI I2C interrupt. The format of the

		    specifier is defined by the binding document describing

		    the node's interrupt parent.



- clocks:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: a list of phandle, should contain an entry for each

		    entries in clock-names.



- clock-names

	Usage: required

	Value type: <string>

	Definition: a list of clock names, must include "cci" clock.



- power-domains

	Usage: required for "qcom,msm8996-cci"

	Value type: <prop-encoded-array>

	Definition:



SUBNODES:



The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and

sdm845), described as subdevices named "i2c-bus@0" and "i2c-bus@1".



PROPERTIES:



- reg:

	Usage: required

	Value type: <u32>

	Definition: Index of the CCI bus/master



- clock-frequency:

	Usage: optional

	Value type: <u32>

	Definition: Desired I2C bus clock frequency in Hz, defaults to 100

		    kHz if omitted.



Example:



	cci@a0c000 {

		compatible = "qcom,msm8996-cci";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xa0c000 0x1000>;

		interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;

		clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,

			 <&mmcc CAMSS_TOP_AHB_CLK>,

			 <&mmcc CAMSS_CCI_AHB_CLK>,

			 <&mmcc CAMSS_CCI_CLK>,

			 <&mmcc CAMSS_AHB_CLK>;

		clock-names = "mmss_mmagic_ahb",

			      "camss_top_ahb",

			      "cci_ahb",

			      "cci",

			      "camss_ahb";



		i2c-bus@0 {

			reg = <0>;

			clock-frequency = <400000>;

			#address-cells = <1>;

			#size-cells = <0>;

		};



		i2c-bus@1 {

			reg = <1>;

			clock-frequency = <400000>;

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};

Documentation/devicetree/bindings/i2c/i2c.txt

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@@ -2,32 +2,26 @@ Generic device tree bindings for I2C busses 
===========================================



This document describes generic bindings which can be used to describe I2C

busses in a device tree.

busses and their child devices in a device tree.



Required properties

-------------------

Required properties (per bus)

-----------------------------



- #address-cells  - should be <1>. Read more about addresses below.

- #size-cells     - should be <0>.

- compatible      - name of I2C bus controller following generic names

		    recommended practice.

- compatible      - name of I2C bus controller



For other required properties e.g. to describe register sets,

clocks, etc. check the binding documentation of the specific driver.



The cells properties above define that an address of children of an I2C bus

are described by a single value. This is usually a 7 bit address. However,

flags can be attached to the address. I2C_TEN_BIT_ADDRESS is used to mark a 10

bit address. It is needed to avoid the ambiguity between e.g. a 7 bit address

of 0x50 and a 10 bit address of 0x050 which, in theory, can be on the same bus.

Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we listen to

be devices ourselves.

are described by a single value.



Optional properties

-------------------

Optional properties (per bus)

-----------------------------



These properties may not be supported by all drivers. However, if a driver

wants to support one of the below features, it should adapt the bindings below.

wants to support one of the below features, it should adapt these bindings.



- clock-frequency

	frequency of bus clock in Hz.
@@ -73,31 +67,54 @@ wants to support one of the below features, it should adapt the bindings below. 
	i2c bus clock frequency (clock-frequency).

	Specified in Hz.



- interrupts

	interrupts used by the device.



- interrupt-names

	"irq", "wakeup" and "smbus_alert" names are recognized by I2C core,

	other names are	left to individual drivers.



- host-notify

	device uses SMBus host notify protocol instead of interrupt line.



- multi-master

	states that there is another master active on this bus. The OS can use

	this information to adapt power management to keep the arbitration awake

	all the time, for example.

	all the time, for example. Can not be combined with 'single-master'.



- wakeup-source

	device can be used as a wakeup source.

- single-master

	states that there is no other master active on this bus. The OS can use

	this information to detect a stalled bus more reliably, for example.

	Can not be combined with 'multi-master'.



Required properties (per child device)

--------------------------------------



- compatible

	name of I2C slave device



- reg

	I2C slave addresses

	One or many I2C slave addresses. These are usually a 7 bit addresses.

	However, flags can be attached to an address. I2C_TEN_BIT_ADDRESS is

	used to mark a 10 bit address. It is needed to avoid the ambiguity

	between e.g. a 7 bit address of 0x50 and a 10 bit address of 0x050

	which, in theory, can be on the same bus.

	Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we

	listen to be devices ourselves.



Optional properties (per child device)

--------------------------------------



These properties may not be supported by all drivers. However, if a driver

wants to support one of the below features, it should adapt these bindings.



- host-notify

	device uses SMBus host notify protocol instead of interrupt line.



- interrupts

	interrupts used by the device.



- interrupt-names

	"irq", "wakeup" and "smbus_alert" names are recognized by I2C core,

	other names are	left to individual drivers.



- reg-names

	Names of map programmable addresses.

	It can contain any map needing another address than default one.



- wakeup-source

	device can be used as a wakeup source.



Binding may contain optional "interrupts" property, describing interrupts

used by the device. I2C core will assign "irq" interrupt (or the very first

interrupt if not using interrupt names) as primary interrupt for the slave.

Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: nuvoton NPCM7XX I2C Controller Device Tree Bindings



description: |

  The NPCM750x includes sixteen I2C bus controllers. All Controllers support

  both master and slave mode. Each controller can switch between master and slave

  at run time (i.e. IPMB mode). Each controller has two 16 byte HW FIFO for TX and

  RX.



maintainers:

  - Tali Perry <tali.perry1@gmail.com>



properties:

  compatible:

    const: nuvoton,npcm7xx-i2c



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1

    description: Reference clock for the I2C bus



  clock-frequency:

    description: Desired I2C bus clock frequency in Hz. If not specified,

                 the default 100 kHz frequency will be used.

                 possible values are 100000, 400000 and 1000000.

    default: 100000

    enum: [100000, 400000, 1000000]



required:

  - compatible

  - reg

  - interrupts

  - clocks



allOf:

  - $ref: /schemas/i2c/i2c-controller.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    i2c0: i2c@80000 {

        reg = <0x80000 0x1000>;

        clocks = <&clk NPCM7XX_CLK_APB2>;

        clock-frequency = <100000>;

        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;

        compatible = "nuvoton,npcm750-i2c";

    };



...

Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml

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# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Synopsys DesignWare APB I2C Controller



maintainers:

  - Jarkko Nikula <jarkko.nikula@linux.intel.com>



allOf:

  - $ref: /schemas/i2c/i2c-controller.yaml#

  - if:

      properties:

        compatible:

          not:

            contains:

              const: mscc,ocelot-i2c

    then:

      properties:

        reg:

          maxItems: 1



properties:

  compatible:

    oneOf:

      - description: Generic Synopsys DesignWare I2C controller

        const: snps,designware-i2c

      - description: Microsemi Ocelot SoCs I2C controller

        items:

          - const: mscc,ocelot-i2c

          - const: snps,designware-i2c

      - description: Baikal-T1 SoC System I2C controller

        const: baikal,bt1-sys-i2c



  reg:

    minItems: 1

    items:

      - description: DW APB I2C controller memory mapped registers

      - description: |

          ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.

          This registers are specific to the Ocelot I2C-controller.



  interrupts:

    maxItems: 1



  clocks:

    minItems: 1

    items:

      - description: I2C controller reference clock source

      - description: APB interface clock source



  clock-names:

    minItems: 1

    items:

      - const: ref

      - const: pclk



  resets:

    maxItems: 1



  clock-frequency:

    description: Desired I2C bus clock frequency in Hz

    enum: [100000, 400000, 1000000, 3400000]

    default: 400000



  i2c-sda-hold-time-ns:

    maxItems: 1

    description: |

      The property should contain the SDA hold time in nanoseconds. This option

      is only supported in hardware blocks version 1.11a or newer or on

      Microsemi SoCs.



  i2c-scl-falling-time-ns:

    maxItems: 1

    description: |

      The property should contain the SCL falling time in nanoseconds.

      This value is used to compute the tLOW period.

    default: 300



  i2c-sda-falling-time-ns:

    maxItems: 1

    description: |

      The property should contain the SDA falling time in nanoseconds.

      This value is used to compute the tHIGH period.

    default: 300



  dmas:

    items:

      - description: TX DMA Channel

      - description: RX DMA Channel



  dma-names:

    items:

      - const: tx

      - const: rx



unevaluatedProperties: false



required:

  - compatible

  - reg

  - "#address-cells"

  - "#size-cells"

  - interrupts



examples:

  - |

    i2c@f0000 {

      compatible = "snps,designware-i2c";

      reg = <0xf0000 0x1000>;

      #address-cells = <1>;

      #size-cells = <0>;

      interrupts = <11>;

      clock-frequency = <400000>;

    };

  - |

    i2c@1120000 {

      compatible = "snps,designware-i2c";

      reg = <0x1120000 0x1000>;

      #address-cells = <1>;

      #size-cells = <0>;

      interrupts = <12 1>;

      clock-frequency = <400000>;

      i2c-sda-hold-time-ns = <300>;

      i2c-sda-falling-time-ns = <300>;

      i2c-scl-falling-time-ns = <300>;

    };

  - |

    i2c@2000 {

      compatible = "snps,designware-i2c";

      reg = <0x2000 0x100>;

      #address-cells = <1>;

      #size-cells = <0>;

      clock-frequency = <400000>;

      clocks = <&i2cclk>;

      interrupts = <0>;



      eeprom@64 {

        compatible = "atmel,24c02";

        reg = <0x64>;

      };

    };

  - |

    i2c@100400 {

      compatible = "mscc,ocelot-i2c", "snps,designware-i2c";

      reg = <0x100400 0x100>, <0x198 0x8>;

      pinctrl-0 = <&i2c_pins>;

      pinctrl-names = "default";

      #address-cells = <1>;

      #size-cells = <0>;

      interrupts = <8>;

      clocks = <&ahb_clk>;

    };

...