Commit 91ec4b0d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS updates from Thomas Bogendoerfer:

 - added support for Huawei B593u-12

 - added support for virt board aligned to QEMU MIPS virt board

 - added support for doing DMA coherence on a per device base

 - reworked handling of RALINK SoCs

 - cleanup for Loongon64 barriers

 - removed deprecated support for MIPS_CMP SMP handling method

 - removed support Sibyte CARMEL and CHRINE boards

 - cleanups and fixes

* tag 'mips_6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (59 commits)
  MIPS: uprobes: Restore thread.trap_nr
  MIPS: Don't clear _PAGE_SPECIAL in _PAGE_CHG_MASK
  MIPS: Sink body of check_bugs_early() into its only call site
  MIPS: Mark check_bugs() as __init
  Revert "MIPS: generic: Enable all CPUs supported by virt board in Kconfig"
  MIPS: octeon_switch: Remove duplicated labels
  MIPS: loongson2ef: Add missing break in cs5536_isa
  MIPS: Remove set_swbp() in uprobes.c
  MIPS: Use def_bool y for ARCH_SUPPORTS_UPROBES
  MIPS: fw: Allow firmware to pass a empty env
  MIPS: Remove deprecated CONFIG_MIPS_CMP
  MIPS: lantiq: remove unused function declaration
  MIPS: Drop unused positional parameter in local_irq_{dis,en}able
  MIPS: mm: Remove local_cache_flush_page
  MIPS: Remove no longer used ide.h
  MIPS: mm: Remove unused *cache_page_indexed flush functions
  MIPS: generic: Enable all CPUs supported by virt board in Kconfig
  MIPS: Add board config for virt board
  MIPS: Octeon: Disable CVMSEG by default on other platforms
  MIPS: Loongson: Don't select platform features with CPU
  ...
parents 513f17f8 46e614cc

Documentation/devicetree/bindings/mips/loongson/devices.yaml

+12 −0
Original line number Diff line number Diff line
@@ -37,6 +37,18 @@ properties: 
        items:

          - const: loongson,loongson64v-4core-virtio



      - description: LS1B based boards

        items:

          - enum:

              - loongson,lsgz-1b-dev

          - const: loongson,ls1b



      - description: LS1C based boards

        items:

          - enum:

              - loongmasses,smartloong-1c

          - const: loongson,ls1c



additionalProperties: true



...

Documentation/devicetree/bindings/vendor-prefixes.yaml

+2 −0
Original line number Diff line number Diff line
@@ -777,6 +777,8 @@ patternProperties: 
    description: Lontium Semiconductor Corporation

  "^loongson,.*":

    description: Loongson Technology Corporation Limited

  "^loongmasses,.*":

    description: Nanjing Loongmasses Ltd.

  "^lsi,.*":

    description: LSI Corp. (LSI Logic)

  "^lwn,.*":

arch/mips/Kbuild.platforms

+0 −1
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ platform-$(CONFIG_SGI_IP30) += sgi-ip30/ 
platform-$(CONFIG_SGI_IP32)		+= sgi-ip32/

platform-$(CONFIG_SIBYTE_BCM112X)	+= sibyte/

platform-$(CONFIG_SIBYTE_SB1250)	+= sibyte/

platform-$(CONFIG_SIBYTE_BCM1x55)	+= sibyte/

platform-$(CONFIG_SIBYTE_BCM1x80)	+= sibyte/

platform-$(CONFIG_SNI_RM)		+= sni/

platform-$(CONFIG_MACH_TX49XX)		+= txx9/

arch/mips/Kconfig

+6 −71
Original line number Diff line number Diff line
@@ -16,7 +16,6 @@ config MIPS 
	select ARCH_HAS_UBSAN_SANITIZE_ALL

	select ARCH_HAS_GCOV_PROFILE_ALL

	select ARCH_KEEP_MEMBLOCK

	select ARCH_SUPPORTS_UPROBES

	select ARCH_USE_BUILTIN_BSWAP

	select ARCH_USE_CMPXCHG_LOCKREF if 64BIT

	select ARCH_USE_MEMTEST
@@ -113,7 +112,6 @@ config MACH_INGENIC 
	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_ZBOOT

	select DMA_NONCOHERENT

	select ARCH_HAS_SYNC_DMA_FOR_CPU

	select IRQ_MIPS_CPU

	select PINCTRL

	select GPIOLIB
@@ -132,7 +130,6 @@ choice 


config MIPS_GENERIC_KERNEL

	bool "Generic board-agnostic MIPS kernel"

	select ARCH_HAS_SETUP_DMA_OPS

	select MIPS_GENERIC

	select BOOT_RAW

	select BUILTIN_DTB
@@ -488,7 +485,6 @@ config MACH_LOONGSON64 
	select BOARD_SCACHE

	select CSRC_R4K

	select CEVT_R4K

	select CPU_HAS_WB

	select FORCE_PCI

	select ISA

	select I8259
@@ -565,7 +561,6 @@ config MIPS_MALTA 
	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_MICROMIPS

	select SYS_SUPPORTS_MIPS16

	select SYS_SUPPORTS_MIPS_CMP

	select SYS_SUPPORTS_MIPS_CPS

	select SYS_SUPPORTS_MULTITHREADING

	select SYS_SUPPORTS_RELOCATABLE
@@ -793,24 +788,6 @@ config SGI_IP32 
	help

	  If you want this kernel to run on SGI O2 workstation, say Y here.



config SIBYTE_CRHINE

	bool "Sibyte BCM91120C-CRhine"

	select BOOT_ELF32

	select SIBYTE_BCM1120

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_SB1

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_LITTLE_ENDIAN



config SIBYTE_CARMEL

	bool "Sibyte BCM91120x-Carmel"

	select BOOT_ELF32

	select SIBYTE_BCM1120

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_SB1

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_LITTLE_ENDIAN



config SIBYTE_CRHONE

	bool "Sibyte BCM91125C-CRhone"

	select BOOT_ELF32
@@ -824,7 +801,7 @@ config SIBYTE_CRHONE 
config SIBYTE_RHONE

	bool "Sibyte BCM91125E-Rhone"

	select BOOT_ELF32

	select SIBYTE_BCM1125H

	select SIBYTE_SB1250

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_SB1

	select SYS_SUPPORTS_BIG_ENDIAN
@@ -1075,7 +1052,7 @@ config FW_CFE 
	bool



config ARCH_SUPPORTS_UPROBES

	bool

	def_bool y



config DMA_NONCOHERENT

	bool
@@ -1086,8 +1063,10 @@ config DMA_NONCOHERENT 
	# by pgprot_writcombine can be mixed, and the latter sometimes provides

	# significant advantages.

	#

	select ARCH_HAS_SETUP_DMA_OPS

	select ARCH_HAS_DMA_WRITE_COMBINE

	select ARCH_HAS_DMA_PREP_COHERENT

	select ARCH_HAS_SYNC_DMA_FOR_CPU

	select ARCH_HAS_SYNC_DMA_FOR_DEVICE

	select ARCH_HAS_DMA_SET_UNCACHED

	select DMA_NONCOHERENT_MMAP
@@ -1181,12 +1160,6 @@ config SYS_SUPPORTS_LITTLE_ENDIAN 
config MIPS_HUGE_TLB_SUPPORT

	def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE



config IRQ_MSP_SLP

	bool



config IRQ_MSP_CIC

	bool



config IRQ_TXX9

	bool
@@ -1364,7 +1337,6 @@ config CPU_LOONGSON2F 
	bool "Loongson 2F"

	depends on SYS_HAS_CPU_LOONGSON2F

	select CPU_LOONGSON2EF

	select GPIOLIB

	help

	  The Loongson 2F processor implements the MIPS III instruction set

	  with many extensions.
@@ -1786,7 +1758,6 @@ config CPU_LOONGSON2EF 
	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_HUGEPAGES

	select ARCH_HAS_PHYS_TO_DMA



config CPU_LOONGSON32

	bool
@@ -1851,11 +1822,9 @@ config SYS_HAS_CPU_MIPS32_R3_5 


config SYS_HAS_CPU_MIPS32_R5

	bool

	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT



config SYS_HAS_CPU_MIPS32_R6

	bool

	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT



config SYS_HAS_CPU_MIPS64_R1

	bool
@@ -1865,15 +1834,12 @@ config SYS_HAS_CPU_MIPS64_R2 


config SYS_HAS_CPU_MIPS64_R5

	bool

	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT



config SYS_HAS_CPU_MIPS64_R6

	bool

	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT



config SYS_HAS_CPU_P5600

	bool

	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT



config SYS_HAS_CPU_R3000

	bool
@@ -1898,7 +1864,6 @@ config SYS_HAS_CPU_NEVADA 


config SYS_HAS_CPU_R10000

	bool

	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT



config SYS_HAS_CPU_RM7000

	bool
@@ -1927,7 +1892,6 @@ config SYS_HAS_CPU_BMIPS4380 
config SYS_HAS_CPU_BMIPS5000

	bool

	select SYS_HAS_CPU_BMIPS

	select ARCH_HAS_SYNC_DMA_FOR_CPU



#

# CPU may reorder R->R, R->W, W->R, W->W
@@ -2298,15 +2262,10 @@ config MIPS_VPE_LOADER 
	  Includes a loader for loading an elf relocatable object

	  onto another VPE and running it.



config MIPS_VPE_LOADER_CMP

	bool

	default "y"

	depends on MIPS_VPE_LOADER && MIPS_CMP



config MIPS_VPE_LOADER_MT

	bool

	default "y"

	depends on MIPS_VPE_LOADER && !MIPS_CMP

	depends on MIPS_VPE_LOADER



config MIPS_VPE_LOADER_TOM

	bool "Load VPE program into memory hidden from linux"
@@ -2322,31 +2281,10 @@ config MIPS_VPE_APSP_API 
	bool "Enable support for AP/SP API (RTLX)"

	depends on MIPS_VPE_LOADER



config MIPS_VPE_APSP_API_CMP

	bool

	default "y"

	depends on MIPS_VPE_APSP_API && MIPS_CMP



config MIPS_VPE_APSP_API_MT

	bool

	default "y"

	depends on MIPS_VPE_APSP_API && !MIPS_CMP



config MIPS_CMP

	bool "MIPS CMP framework support (DEPRECATED)"

	depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6

	select SMP

	select SYNC_R4K

	select SYS_SUPPORTS_SMP

	select WEAK_ORDERING

	default n

	help

	  Select this if you are using a bootloader which implements the "CMP

	  framework" protocol (ie. YAMON) and want your kernel to make use of

	  its ability to start secondary CPUs.



	  Unless you have a specific need, you should use CONFIG_MIPS_CPS

	  instead of this.

	depends on MIPS_VPE_APSP_API



config MIPS_CPS

	bool "MIPS Coherent Processing System support"
@@ -2802,9 +2740,6 @@ config HOTPLUG_CPU 
config SMP_UP

	bool



config SYS_SUPPORTS_MIPS_CMP

	bool



config SYS_SUPPORTS_MIPS_CPS

	bool

arch/mips/Makefile

+38 −0
Original line number Diff line number Diff line
@@ -181,9 +181,47 @@ endif 
cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1

cflags-$(CONFIG_CPU_BMIPS)	+= -march=mips32 -Wa,-mips32 -Wa,--trap



cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap

cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap

# Some -march= flags enable MMI instructions, and GCC complains about that

# support being enabled alongside -msoft-float. Thus explicitly disable MMI.

cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi)

ifdef CONFIG_CPU_LOONGSON64

cflags-$(CONFIG_CPU_LOONGSON64)	+= -Wa,--trap

cflags-$(CONFIG_CC_IS_GCC) += -march=loongson3a

cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2

endif

cflags-$(CONFIG_CPU_LOONGSON64) += $(call cc-option,-mno-loongson-mmi)



cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)	+= $(call cc-option,-mfix-r4000,)

cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= $(call cc-option,-mfix-r4400,)

cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS)	+= $(call cc-option,-mno-daddi,)

ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS

cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop

cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump

endif



#

# Some versions of binutils, not currently mainline as of 2019/02/04, support

# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction

# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a

# description).

#

# We disable this in order to prevent the assembler meddling with the

# instruction that labels refer to, ie. if we label an ll instruction:

#

# 1: ll v0, 0(a0)

#

# ...then with the assembler fix applied the label may actually point at a sync

# instruction inserted by the assembler, and if we were using the label in an

# exception table the table would no longer contain the address of the ll

# instruction.

#

# Avoid this by explicitly disabling that assembler behaviour. If upstream

# binutils does not merge support for the flag then we can revisit & remove

# this later - for now it ensures vendor toolchains don't cause problems.

#

cflags-$(CONFIG_CPU_LOONGSON64)	+= $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)



# For smartmips configurations, there are hundreds of warnings due to ISA overrides

# in assembly and header files. smartmips is only supported for MIPS32r1 onwards