Commit 91e9ee7e authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/32s: Rename PTE_SIZE to PTE_T_SIZE 



PTE_SIZE means PTE page table size in most placed, whereas
in hash_low.S in means size of one entry in the table.

Rename it PTE_T_SIZE, and define it directly in hash_low.S
instead of going through asm-offsets.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/83a008a9fd6cc3f2bbcb470f592555d260ed7a3d.1623063174.git.christophe.leroy@csgroup.eu
parent e72421a0

arch/powerpc/kernel/asm-offsets.c

+0 −2
Original line number Diff line number Diff line
@@ -354,8 +354,6 @@ int main(void) 
	DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));

#endif



	DEFINE(PTE_SIZE, sizeof(pte_t));



#ifdef CONFIG_KVM

	OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);

	OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);

arch/powerpc/mm/book3s32/hash_low.S

+4 −2
Original line number Diff line number Diff line
@@ -27,8 +27,10 @@ 
#include <asm/code-patching-asm.h>



#ifdef CONFIG_PTE_64BIT

#define PTE_T_SIZE		8

#define PTE_FLAGS_OFFSET	4	/* offset of PTE flags, in bytes */

#else

#define PTE_T_SIZE		4

#define PTE_FLAGS_OFFSET	0

#endif
@@ -488,7 +490,7 @@ _GLOBAL(flush_hash_pages) 
	bne	2f

	ble	cr1,19f

	addi	r4,r4,0x1000

	addi	r5,r5,PTE_SIZE

	addi	r5,r5,PTE_T_SIZE

	addi	r6,r6,-1

	b	1b
@@ -573,7 +575,7 @@ _GLOBAL(flush_hash_pages) 


8:	ble	cr1,9f			/* if all ptes checked */

81:	addi	r6,r6,-1

	addi	r5,r5,PTE_SIZE

	addi	r5,r5,PTE_T_SIZE

	addi	r4,r4,0x1000

	lwz	r0,0(r5)		/* check next pte */

	cmpwi	cr1,r6,1