Commit 91e2ca22 authored by Mårten Lindahl's avatar Mårten Lindahl Committed by Ulf Hansson
Browse files

mmc: dw_mmc-exynos: Add support for ARTPEC-8 



The ARTPEC-8 SoC has a DWMMC controller that is compatible with the
Exynos 7 version v2.70a. The main differences from Exynos 7 is that it
does not support HS400 and has extended data read timeout.

This patch adds compatibility string "axis,artpec8-dw-mshc" for
ARTPEC-8, and DW_MCI_TYPE_ARTPEC8 is added to the dw_mci_exynos_type.

Signed-off-by: default avatarMårten Lindahl <marten.lindahl@axis.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211220113026.21129-3-marten.lindahl@axis.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent d7d87484

drivers/mmc/host/dw_mmc-exynos.c

+36 −11
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ enum dw_mci_exynos_type { 
	DW_MCI_TYPE_EXYNOS5420_SMU,

	DW_MCI_TYPE_EXYNOS7,

	DW_MCI_TYPE_EXYNOS7_SMU,

	DW_MCI_TYPE_ARTPEC8,

};



/* Exynos implementation specific driver private data */
@@ -69,6 +70,9 @@ static struct dw_mci_exynos_compatible { 
	}, {

		.compatible	= "samsung,exynos7-dw-mshc-smu",

		.ctrl_type	= DW_MCI_TYPE_EXYNOS7_SMU,

	}, {

		.compatible	= "axis,artpec8-dw-mshc",

		.ctrl_type	= DW_MCI_TYPE_ARTPEC8,

	},

};
@@ -81,7 +85,8 @@ static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host) 
	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)

		return EXYNOS4210_FIXED_CIU_CLK_DIV;

	else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||

			priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)

			priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||

			priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)

		return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;

	else

		return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
@@ -133,7 +138,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) 
	u32 clksel;



	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||

		priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)

		clksel = mci_readl(host, CLKSEL64);

	else

		clksel = mci_readl(host, CLKSEL);
@@ -141,7 +147,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) 
	clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;



	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||

		priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)

		mci_writel(host, CLKSEL64, clksel);

	else

		mci_writel(host, CLKSEL, clksel);
@@ -210,14 +217,16 @@ static int dw_mci_exynos_resume_noirq(struct device *dev) 
		return ret;



	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||

		priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)

		clksel = mci_readl(host, CLKSEL64);

	else

		clksel = mci_readl(host, CLKSEL);



	if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {

		if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||

			priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)

			priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||

			priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)

			mci_writel(host, CLKSEL64, clksel);

		else

			mci_writel(host, CLKSEL, clksel);
@@ -238,7 +247,8 @@ static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing) 
	 * Not supported to configure register

	 * related to HS400

	 */

	if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) {

	if ((priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) ||

		(priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)) {

		if (timing == MMC_TIMING_MMC_HS400)

			dev_warn(host->dev,

				 "cannot configure HS400, unsupported chipset\n");
@@ -394,7 +404,8 @@ static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host) 
	struct dw_mci_exynos_priv_data *priv = host->priv;



	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||

		priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)

		return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));

	else

		return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
@@ -406,13 +417,15 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) 
	struct dw_mci_exynos_priv_data *priv = host->priv;



	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||

		priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)

		clksel = mci_readl(host, CLKSEL64);

	else

		clksel = mci_readl(host, CLKSEL);

	clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);

	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||

		priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)

		mci_writel(host, CLKSEL64, clksel);

	else

		mci_writel(host, CLKSEL, clksel);
@@ -425,7 +438,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) 
	u8 sample;



	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||

		priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)

		clksel = mci_readl(host, CLKSEL64);

	else

		clksel = mci_readl(host, CLKSEL);
@@ -434,7 +448,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) 
	clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);



	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)

		priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||

		priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)

		mci_writel(host, CLKSEL64, clksel);

	else

		mci_writel(host, CLKSEL, clksel);
@@ -543,6 +558,14 @@ static const struct dw_mci_drv_data exynos_drv_data = { 
	.prepare_hs400_tuning	= dw_mci_exynos_prepare_hs400_tuning,

};



static const struct dw_mci_drv_data artpec_drv_data = {

	.common_caps		= MMC_CAP_CMD23,

	.init			= dw_mci_exynos_priv_init,

	.set_ios		= dw_mci_exynos_set_ios,

	.parse_dt		= dw_mci_exynos_parse_dt,

	.execute_tuning		= dw_mci_exynos_execute_tuning,

};



static const struct of_device_id dw_mci_exynos_match[] = {

	{ .compatible = "samsung,exynos4412-dw-mshc",

			.data = &exynos_drv_data, },
@@ -556,6 +579,8 @@ static const struct of_device_id dw_mci_exynos_match[] = { 
			.data = &exynos_drv_data, },

	{ .compatible = "samsung,exynos7-dw-mshc-smu",

			.data = &exynos_drv_data, },

	{ .compatible = "axis,artpec8-dw-mshc",

			.data = &artpec_drv_data, },

	{},

};

MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);