Commit 91db7a3f authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Mauro Carvalho Chehab
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media: cedrus: Fix endless loop in cedrus_h265_skip_bits() 



The busy status bit may never de-assert if number of programmed skip
bits is incorrect, resulting in a kernel hang because the bit is polled
endlessly in the code. Fix it by adding timeout for the bit-polling.
This problem is reproducible by setting the data_bit_offset field of
the HEVC slice params to a wrong value by userspace.

Cc: stable@vger.kernel.org
Fixes: 7678c546 (media: cedrus: Fix decoding for some HEVC videos)
Reported-by: default avatarNicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: default avatarDmitry Osipenko <dmitry.osipenko@collabora.com>
Signed-off-by: default avatarNicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@kernel.org>
parent 708938f8

drivers/staging/media/sunxi/cedrus/cedrus_h265.c

+3 −2
Original line number Diff line number Diff line
@@ -234,8 +234,9 @@ static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num) 
		cedrus_write(dev, VE_DEC_H265_TRIGGER,

			     VE_DEC_H265_TRIGGER_FLUSH_BITS |

			     VE_DEC_H265_TRIGGER_TYPE_N_BITS(tmp));

		while (cedrus_read(dev, VE_DEC_H265_STATUS) & VE_DEC_H265_STATUS_VLD_BUSY)

			udelay(1);



		if (cedrus_wait_for(dev, VE_DEC_H265_STATUS, VE_DEC_H265_STATUS_VLD_BUSY))

			dev_err_ratelimited(dev->dev, "timed out waiting to skip bits\n");



		count += tmp;

	}