Commit 91d248c3 authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

tools arch x86: Sync the msr-index.h copy with the kernel sources 

To pick up the changes from these csets:

  4ad3278d ("x86/speculation: Disable RRSBA behavior")
  d7caac99 ("x86/cpu/amd: Add Spectral Chicken")

That cause no changes to tooling:

  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before
  $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after
  $ diff -u before after
  $

Just silences this perf build warning:

  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/msr-index.h' differs from latest version at 'arch/x86/include/asm/msr-index.h'
  diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/lkml/YtQTm9wsB3hxQWvy@kernel.org


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent f098addb

tools/arch/x86/include/asm/msr-index.h

+4 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ 
#define MSR_IA32_ARCH_CAPABILITIES	0x0000010a

#define ARCH_CAP_RDCL_NO		BIT(0)	/* Not susceptible to Meltdown */

#define ARCH_CAP_IBRS_ALL		BIT(1)	/* Enhanced IBRS support */

#define ARCH_CAP_RSBA			BIT(2)	/* RET may use alternative branch predictors */

#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH	BIT(3)	/* Skip L1D flush on vmentry */

#define ARCH_CAP_SSB_NO			BIT(4)	/*

						 * Not susceptible to Speculative Store Bypass
@@ -576,6 +577,9 @@ 
/* Fam 17h MSRs */

#define MSR_F17H_IRPERF			0xc00000e9



#define MSR_ZEN2_SPECTRAL_CHICKEN	0xc00110e3

#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT	BIT_ULL(1)



/* Fam 16h MSRs */

#define MSR_F16H_L2I_PERF_CTL		0xc0010230

#define MSR_F16H_L2I_PERF_CTR		0xc0010231