Commit 91c6945e authored by Hariprasad Kelam's avatar Hariprasad Kelam Committed by David S. Miller
Browse files

octeontx2-af: cn10k: Add RPM MAC support 



OcteonTx2's next gen platform the CN10K has RPM MAC which has a
different serdes when compared to CGX MAC. Though the underlying
HW is different, the CSR interface has been designed largely inline
with CGX MAC, with few exceptions though. So we are using the same
CGX driver for RPM MAC as well and will have a different set of APIs
for RPM where ever necessary.

This patch adds initial support for CN10K's RPM MAC i.e. the driver
registration, communication with firmware etc. For communication with
firmware, RPM provides a different IRQ when compared to CGX.
The CGX and RPM blocks support different features. Currently few
features like ptp, flowcontrol and higig are not supported by RPM. This
patch adds new mailbox message "CGX_FEATURES_GET" to get the list of
features supported by underlying MAC.

RPM has different implementations for RX/TX stats. Unlike CGX,
bar offset of stat registers are different. This patch adds
support to access the same and dump the values in debugfs.

Signed-off-by: default avatarHariprasad Kelam <hkelam@marvell.com>
Signed-off-by: default avatarSubbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: default avatarGeetha sowjanya <gakula@marvell.com>
Signed-off-by: default avatarSunil Goutham <sgoutham@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4c236d5d

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -10719,6 +10719,7 @@ M: Sunil Goutham <sgoutham@marvell.com> 
M:	Linu Cherian <lcherian@marvell.com>

M:	Geetha sowjanya <gakula@marvell.com>

M:	Jerin Jacob <jerinj@marvell.com>

M:	hariprasad <hkelam@marvell.com>

L:	netdev@vger.kernel.org

S:	Supported

F:	Documentation/networking/device_drivers/ethernet/marvell/octeontx2.rst

drivers/net/ethernet/marvell/octeontx2/af/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -10,4 +10,4 @@ obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o 
octeontx2_mbox-y := mbox.o rvu_trace.o

octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \

		  rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \

		  rvu_cpt.o rvu_devlink.o
 
		  rvu_cpt.o rvu_devlink.o rpm.o

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

+191 −80
Original line number Diff line number Diff line
@@ -21,47 +21,11 @@ 
#include <linux/of_net.h>



#include "cgx.h"

#include "rvu.h"

#include "lmac_common.h"



#define DRV_NAME	"octeontx2-cgx"

#define DRV_STRING      "Marvell OcteonTX2 CGX/MAC Driver"



/**

 * struct lmac

 * @wq_cmd_cmplt:	waitq to keep the process blocked until cmd completion

 * @cmd_lock:		Lock to serialize the command interface

 * @resp:		command response

 * @link_info:		link related information

 * @event_cb:		callback for linkchange events

 * @event_cb_lock:	lock for serializing callback with unregister

 * @cmd_pend:		flag set before new command is started

 *			flag cleared after command response is received

 * @cgx:		parent cgx port

 * @lmac_id:		lmac port id

 * @name:		lmac port name

 */

struct lmac {

	wait_queue_head_t wq_cmd_cmplt;

	struct mutex cmd_lock;

	u64 resp;

	struct cgx_link_user_info link_info;

	struct cgx_event_cb event_cb;

	spinlock_t event_cb_lock;

	bool cmd_pend;

	struct cgx *cgx;

	u8 lmac_id;

	char *name;

};



struct cgx {

	void __iomem		*reg_base;

	struct pci_dev		*pdev;

	u8			cgx_id;

	u8			lmac_count;

	struct lmac		*lmac_idmap[MAX_LMAC_PER_CGX];

	struct			work_struct cgx_cmd_work;

	struct			workqueue_struct *cgx_cmd_workq;

	struct list_head	cgx_list;

};

#define DRV_NAME	"Marvell-CGX/RPM"

#define DRV_STRING      "Marvell CGX/RPM Driver"



static LIST_HEAD(cgx_list);
@@ -77,22 +41,45 @@ static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en); 
/* Supported devices */

static const struct pci_device_id cgx_id_table[] = {

	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },

	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM) },

	{ 0, }  /* end of table */

};



MODULE_DEVICE_TABLE(pci, cgx_id_table);



static void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val)

static bool is_dev_rpm(void *cgxd)

{

	struct cgx *cgx = cgxd;



	return (cgx->pdev->device == PCI_DEVID_CN10K_RPM);

}



bool is_lmac_valid(struct cgx *cgx, int lmac_id)

{

	writeq(val, cgx->reg_base + (lmac << 18) + offset);

	return cgx && test_bit(lmac_id, &cgx->lmac_bmap);

}



static u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset)

struct mac_ops *get_mac_ops(void *cgxd)

{

	return readq(cgx->reg_base + (lmac << 18) + offset);

	if (!cgxd)

		return cgxd;



	return ((struct cgx *)cgxd)->mac_ops;

}



void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val)

{

	writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +

	       offset);

}



static inline struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx)

u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset)

{

	return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +

		     offset);

}



struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx)

{

	if (!cgx || lmac_id >= MAX_LMAC_PER_CGX)

		return NULL;
@@ -186,8 +173,10 @@ static u64 mac2u64 (u8 *mac_addr) 
int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr)

{

	struct cgx *cgx_dev = cgx_get_pdata(cgx_id);

	struct mac_ops *mac_ops;

	u64 cfg;



	mac_ops = cgx_dev->mac_ops;

	/* copy 6bytes from macaddr */

	/* memcpy(&cfg, mac_addr, 6); */
@@ -206,8 +195,11 @@ int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr) 
u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id)

{

	struct cgx *cgx_dev = cgx_get_pdata(cgx_id);

	struct mac_ops *mac_ops;

	u64 cfg;



	mac_ops = cgx_dev->mac_ops;



	cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8);

	return cfg & CGX_RX_DMAC_ADR_MASK;

}
@@ -216,7 +208,7 @@ int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind) 
{

	struct cgx *cgx = cgxd;



	if (!cgx || lmac_id >= cgx->lmac_count)

	if (!is_lmac_valid(cgx, lmac_id))

		return -ENODEV;



	cgx_write(cgx, lmac_id, CGXX_CMRX_RX_ID_MAP, (pkind & 0x3F));
@@ -238,7 +230,7 @@ int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable) 
	u8 lmac_type;

	u64 cfg;



	if (!cgx || lmac_id >= cgx->lmac_count)

	if (!is_lmac_valid(cgx, lmac_id))

		return -ENODEV;



	lmac_type = cgx_get_lmac_type(cgx, lmac_id);
@@ -263,11 +255,13 @@ int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable) 
void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable)

{

	struct cgx *cgx = cgx_get_pdata(cgx_id);

	struct mac_ops *mac_ops;

	u64 cfg = 0;



	if (!cgx)

		return;



	mac_ops = cgx->mac_ops;

	if (enable) {

		/* Enable promiscuous mode on LMAC */

		cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
@@ -299,6 +293,9 @@ void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable) 
	struct cgx *cgx = cgxd;

	u64 cfg;



	if (is_dev_rpm(cgx))

		return;



	if (!cgx)

		return;
@@ -323,9 +320,11 @@ void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable) 


int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat)

{

	struct mac_ops *mac_ops;

	struct cgx *cgx = cgxd;



	if (!cgx || lmac_id >= cgx->lmac_count)

	mac_ops = cgx->mac_ops;

	if (!is_lmac_valid(cgx, lmac_id))

		return -ENODEV;

	*rx_stat =  cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8));

	return 0;
@@ -333,14 +332,21 @@ int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat) 


int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat)

{

	struct mac_ops *mac_ops;

	struct cgx *cgx = cgxd;



	if (!cgx || lmac_id >= cgx->lmac_count)

	mac_ops = cgx->mac_ops;

	if (!is_lmac_valid(cgx, lmac_id))

		return -ENODEV;

	*tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8));

	return 0;

}



u64 cgx_features_get(void *cgxd)

{

	return ((struct cgx *)cgxd)->hw_features;

}



static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo)

{

	if (!linfo->fec)
@@ -400,7 +406,7 @@ int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable) 
	struct cgx *cgx = cgxd;

	u64 cfg;



	if (!cgx || lmac_id >= cgx->lmac_count)

	if (!is_lmac_valid(cgx, lmac_id))

		return -ENODEV;



	cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
@@ -417,7 +423,7 @@ int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable) 
	struct cgx *cgx = cgxd;

	u64 cfg, last;



	if (!cgx || lmac_id >= cgx->lmac_count)

	if (!is_lmac_valid(cgx, lmac_id))

		return -ENODEV;



	cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
@@ -438,7 +444,10 @@ int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id, 
	struct cgx *cgx = cgxd;

	u64 cfg;



	if (!cgx || lmac_id >= cgx->lmac_count)

	if (is_dev_rpm(cgx))

		return 0;



	if (!is_lmac_valid(cgx, lmac_id))

		return -ENODEV;



	cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
@@ -455,7 +464,10 @@ int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id, 
	struct cgx *cgx = cgxd;

	u64 cfg;



	if (!cgx || lmac_id >= cgx->lmac_count)

	if (is_dev_rpm(cgx))

		return 0;



	if (!is_lmac_valid(cgx, lmac_id))

		return -ENODEV;



	cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
@@ -483,7 +495,10 @@ static void cgx_lmac_pause_frm_config(struct cgx *cgx, int lmac_id, bool enable) 
{

	u64 cfg;



	if (!cgx || lmac_id >= cgx->lmac_count)

	if (is_dev_rpm(cgx))

		return;



	if (!is_lmac_valid(cgx, lmac_id))

		return;

	if (enable) {

		/* Enable receive pause frames */
@@ -541,6 +556,9 @@ void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable) 
	if (!cgx)

		return;



	if (is_dev_rpm(cgx))

		return;



	if (enable) {

		/* Enable inbound PTP timestamping */

		cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
@@ -563,7 +581,7 @@ void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable) 
}



/* CGX Firmware interface low level support */

static int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac)

int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac)

{

	struct cgx *cgx = lmac->cgx;

	struct device *dev;
@@ -611,8 +629,7 @@ static int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac) 
	return err;

}



static inline int cgx_fwi_cmd_generic(u64 req, u64 *resp,

				      struct cgx *cgx, int lmac_id)

int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id)

{

	struct lmac *lmac;

	int err;
@@ -885,12 +902,16 @@ static inline bool cgx_event_is_linkevent(u64 event) 


static irqreturn_t cgx_fwi_event_handler(int irq, void *data)

{

	u64 event, offset, clear_bit;

	struct lmac *lmac = data;

	struct cgx *cgx;

	u64 event;



	cgx = lmac->cgx;



	/* Clear SW_INT for RPM and CMR_INT for CGX */

	offset     = cgx->mac_ops->int_register;

	clear_bit  = cgx->mac_ops->int_ena_bit;



	event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG);



	if (!FIELD_GET(EVTREG_ACK, event))
@@ -926,7 +947,7 @@ static irqreturn_t cgx_fwi_event_handler(int irq, void *data) 
	 * Ack the interrupt register as well.

	 */

	cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0);

	cgx_write(lmac->cgx, lmac->lmac_id, CGXX_CMRX_INT, FW_CGX_INT);

	cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit);



	return IRQ_HANDLED;

}
@@ -970,14 +991,16 @@ int cgx_get_fwdata_base(u64 *base) 
{

	u64 req = 0, resp;

	struct cgx *cgx;

	int first_lmac;

	int err;



	cgx = list_first_entry_or_null(&cgx_list, struct cgx, cgx_list);

	if (!cgx)

		return -ENXIO;



	first_lmac = find_first_bit(&cgx->lmac_bmap, MAX_LMAC_PER_CGX);

	req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req);

	err = cgx_fwi_cmd_generic(req, &resp, cgx, 0);

	err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac);

	if (!err)

		*base = FIELD_GET(RESP_FWD_BASE, resp);
@@ -1056,10 +1079,11 @@ static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable) 


static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx)

{

	int first_lmac = find_first_bit(&cgx->lmac_bmap, MAX_LMAC_PER_CGX);

	u64 req = 0;



	req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req);

	return cgx_fwi_cmd_generic(req, resp, cgx, 0);

	return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac);

}



static int cgx_lmac_verify_fwi_version(struct cgx *cgx)
@@ -1092,8 +1116,8 @@ static void cgx_lmac_linkup_work(struct work_struct *work) 
	struct device *dev = &cgx->pdev->dev;

	int i, err;



	/* Do Link up for all the lmacs */

	for (i = 0; i < cgx->lmac_count; i++) {

	/* Do Link up for all the enabled lmacs */

	for_each_set_bit(i, &cgx->lmac_bmap, MAX_LMAC_PER_CGX) {

		err = cgx_fwi_link_change(cgx, i, true);

		if (err)

			dev_info(dev, "cgx port %d:%d Link up command failed\n",
@@ -1113,12 +1137,67 @@ int cgx_lmac_linkup_start(void *cgxd) 
	return 0;

}



static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac,

				   int cnt, bool req_free)

{

	struct mac_ops *mac_ops = cgx->mac_ops;

	u64 offset, ena_bit;

	unsigned int irq;

	int err;



	irq      = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi +

				  cnt * mac_ops->irq_offset);

	offset   = mac_ops->int_set_reg;

	ena_bit  = mac_ops->int_ena_bit;



	if (req_free) {

		free_irq(irq, lmac);

		return 0;

	}



	err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac);

	if (err)

		return err;



	/* Enable interrupt */

	cgx_write(cgx, lmac->lmac_id, offset, ena_bit);

	return 0;

}



int cgx_get_nr_lmacs(void *cgxd)

{

	struct cgx *cgx = cgxd;



	return cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7ULL;

}



u8 cgx_get_lmacid(void *cgxd, u8 lmac_index)

{

	struct cgx *cgx = cgxd;



	return cgx->lmac_idmap[lmac_index]->lmac_id;

}



unsigned long cgx_get_lmac_bmap(void *cgxd)

{

	struct cgx *cgx = cgxd;



	return cgx->lmac_bmap;

}



static int cgx_lmac_init(struct cgx *cgx)

{

	struct lmac *lmac;

	u64 lmac_list;

	int i, err;



	cgx->lmac_count = cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7;

	cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx);

	/* lmac_list specifies which lmacs are enabled

	 * when bit n is set to 1, LMAC[n] is enabled

	 */

	if (cgx->mac_ops->non_contiguous_serdes_lane)

		lmac_list = cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0xFULL;



	if (cgx->lmac_count > MAX_LMAC_PER_CGX)

		cgx->lmac_count = MAX_LMAC_PER_CGX;
@@ -1132,24 +1211,25 @@ static int cgx_lmac_init(struct cgx *cgx) 
			goto err_lmac_free;

		}

		sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i);

		if (cgx->mac_ops->non_contiguous_serdes_lane) {

			lmac->lmac_id = __ffs64(lmac_list);

			lmac_list   &= ~BIT_ULL(lmac->lmac_id);

		} else {

			lmac->lmac_id = i;

		}



		lmac->cgx = cgx;

		init_waitqueue_head(&lmac->wq_cmd_cmplt);

		mutex_init(&lmac->cmd_lock);

		spin_lock_init(&lmac->event_cb_lock);

		err = request_irq(pci_irq_vector(cgx->pdev,

						 CGX_LMAC_FWI + i * 9),

				   cgx_fwi_event_handler, 0, lmac->name, lmac);

		err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false);

		if (err)

			goto err_irq;



		/* Enable interrupt */

		cgx_write(cgx, lmac->lmac_id, CGXX_CMRX_INT_ENA_W1S,

			  FW_CGX_INT);



		/* Add reference */

		cgx->lmac_idmap[i] = lmac;

		cgx_lmac_pause_frm_config(cgx, i, true);

		cgx->lmac_idmap[lmac->lmac_id] = lmac;

		cgx_lmac_pause_frm_config(cgx, lmac->lmac_id, true);

		set_bit(lmac->lmac_id, &cgx->lmac_bmap);

	}



	return cgx_lmac_verify_fwi_version(cgx);
@@ -1173,12 +1253,12 @@ static int cgx_lmac_exit(struct cgx *cgx) 
	}



	/* Free all lmac related resources */

	for (i = 0; i < cgx->lmac_count; i++) {

		cgx_lmac_pause_frm_config(cgx, i, false);

	for_each_set_bit(i, &cgx->lmac_bmap, MAX_LMAC_PER_CGX) {

		lmac = cgx->lmac_idmap[i];

		if (!lmac)

			continue;

		free_irq(pci_irq_vector(cgx->pdev, CGX_LMAC_FWI + i * 9), lmac);

		cgx_lmac_pause_frm_config(cgx, lmac->lmac_id, false);

		cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true);

		kfree(lmac->name);

		kfree(lmac);

	}
@@ -1186,6 +1266,27 @@ static int cgx_lmac_exit(struct cgx *cgx) 
	return 0;

}



static void cgx_populate_features(struct cgx *cgx)

{

	if (is_dev_rpm(cgx))

		cgx->hw_features =  RVU_MAC_RPM;

	else

		cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP);

}



static struct mac_ops	cgx_mac_ops    = {

	.name		=       "cgx",

	.csr_offset	=       0,

	.lmac_offset    =       18,

	.int_register	=       CGXX_CMRX_INT,

	.int_set_reg	=       CGXX_CMRX_INT_ENA_W1S,

	.irq_offset	=       9,

	.int_ena_bit    =       FW_CGX_INT,

	.lmac_fwi	=	CGX_LMAC_FWI,

	.non_contiguous_serdes_lane = false,

	.get_nr_lmacs	=	cgx_get_nr_lmacs,

};



static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)

{

	struct device *dev = &pdev->dev;
@@ -1199,6 +1300,12 @@ static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id) 


	pci_set_drvdata(pdev, cgx);



	/* Use mac_ops to get MAC specific features */

	if (pdev->device == PCI_DEVID_CN10K_RPM)

		cgx->mac_ops = rpm_get_mac_ops();

	else

		cgx->mac_ops = &cgx_mac_ops;



	err = pci_enable_device(pdev);

	if (err) {

		dev_err(dev, "Failed to enable PCI device\n");
@@ -1220,7 +1327,7 @@ static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
		goto err_release_regions;

	}



	nvec = CGX_NVEC;

	nvec = pci_msix_vec_count(cgx->pdev);

	err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);

	if (err < 0 || err != nvec) {

		dev_err(dev, "Request for %d msix vectors failed, err %d\n",
@@ -1244,6 +1351,8 @@ static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id) 


	cgx_link_usertable_init();



	cgx_populate_features(cgx);



	err = cgx_lmac_init(cgx);

	if (err)

		goto err_release_lmac;
@@ -1267,8 +1376,10 @@ static void cgx_remove(struct pci_dev *pdev) 
{

	struct cgx *cgx = pci_get_drvdata(pdev);



	if (cgx) {

		cgx_lmac_exit(cgx);

		list_del(&cgx->cgx_list);

	}

	pci_free_irq_vectors(pdev);

	pci_release_regions(pdev);

	pci_disable_device(pdev);

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

+10 −6
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 


#include "mbox.h"

#include "cgx_fw_if.h"

#include "rpm.h"



 /* PCI device IDs */

#define	PCI_DEVID_OCTEONTX2_CGX		0xA059
@@ -40,18 +41,18 @@ 
#define FW_CGX_INT			BIT_ULL(1)

#define CGXX_CMRX_INT_ENA_W1S		0x058

#define CGXX_CMRX_RX_ID_MAP		0x060

#define CGXX_CMRX_RX_STAT0		0x070

#define CGXX_CMRX_RX_STAT0		(0x070 + mac_ops->csr_offset)

#define CGXX_CMRX_RX_LMACS		0x128

#define CGXX_CMRX_RX_DMAC_CTL0		0x1F8

#define CGXX_CMRX_RX_DMAC_CTL0		(0x1F8 + mac_ops->csr_offset)

#define CGX_DMAC_CTL0_CAM_ENABLE	BIT_ULL(3)

#define CGX_DMAC_CAM_ACCEPT		BIT_ULL(3)

#define CGX_DMAC_MCAST_MODE		BIT_ULL(1)

#define CGX_DMAC_BCAST_MODE		BIT_ULL(0)

#define CGXX_CMRX_RX_DMAC_CAM0		0x200

#define CGXX_CMRX_RX_DMAC_CAM0		(0x200 + mac_ops->csr_offset)

#define CGX_DMAC_CAM_ADDR_ENABLE	BIT_ULL(48)

#define CGXX_CMRX_RX_DMAC_CAM1		0x400

#define CGX_RX_DMAC_ADR_MASK		GENMASK_ULL(47, 0)

#define CGXX_CMRX_TX_STAT0		0x700

#define CGXX_CMRX_TX_STAT0		(0x700 + mac_ops->csr_offset)

#define CGXX_SCRATCH0_REG		0x1050

#define CGXX_SCRATCH1_REG		0x1058

#define CGX_CONST			0x2000
@@ -86,7 +87,6 @@ 
#define CGX_CMD_TIMEOUT			2200 /* msecs */

#define DEFAULT_PAUSE_TIME		0x7FF



#define CGX_NVEC			37

#define CGX_LMAC_FWI			0



enum  cgx_nix_stat_type {
@@ -157,5 +157,9 @@ int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp); 
int cgx_get_phy_fec_stats(void *cgxd, int lmac_id);

int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,

		      int cgx_id, int lmac_id);



u64 cgx_features_get(void *cgxd);

struct mac_ops *get_mac_ops(void *cgxd);

int cgx_get_nr_lmacs(void *cgxd);

u8 cgx_get_lmacid(void *cgxd, u8 lmac_index);

unsigned long cgx_get_lmac_bmap(void *cgxd);

#endif /* CGX_H */

drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h

0 → 100644
+96 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*  Marvell OcteonTx2 RPM driver

 *

 * Copyright (C) 2020 Marvell.

 */



#ifndef LMAC_COMMON_H

#define LMAC_COMMON_H



#include "rvu.h"

#include "cgx.h"

/**

 * struct lmac

 * @wq_cmd_cmplt:	waitq to keep the process blocked until cmd completion

 * @cmd_lock:		Lock to serialize the command interface

 * @resp:		command response

 * @link_info:		link related information

 * @event_cb:		callback for linkchange events

 * @event_cb_lock:	lock for serializing callback with unregister

 * @cmd_pend:		flag set before new command is started

 *			flag cleared after command response is received

 * @cgx:		parent cgx port

 * @lmac_id:		lmac port id

 * @name:		lmac port name

 */

struct lmac {

	wait_queue_head_t wq_cmd_cmplt;

	/* Lock to serialize the command interface */

	struct mutex cmd_lock;

	u64 resp;

	struct cgx_link_user_info link_info;

	struct cgx_event_cb event_cb;

	/* lock for serializing callback with unregister */

	spinlock_t event_cb_lock;

	bool cmd_pend;

	struct cgx *cgx;

	u8 lmac_id;

	char *name;

};



/* CGX & RPM has different feature set

 * update the structure fields with different one

 */

struct mac_ops {

	char		       *name;

	/* Features like RXSTAT, TXSTAT, DMAC FILTER csrs differs by fixed

	 * bar offset for example

	 * CGX DMAC_CTL0  0x1f8

	 * RPM DMAC_CTL0  0x4ff8

	 */

	u64			csr_offset;

	/* For ATF to send events to kernel, there is no dedicated interrupt

	 * defined hence CGX uses OVERFLOW bit in CMR_INT. RPM block supports

	 * SW_INT so that ATF triggers this interrupt after processing of

	 * requested command

	 */

	u64			int_register;

	u64			int_set_reg;

	/* lmac offset is different is RPM */

	u8			lmac_offset;

	u8			irq_offset;

	u8			int_ena_bit;

	u8			lmac_fwi;

	bool			non_contiguous_serdes_lane;

	/* Incase of RPM get number of lmacs from RPMX_CMR_RX_LMACS[LMAC_EXIST]

	 * number of setbits in lmac_exist tells number of lmacs

	 */

	int			(*get_nr_lmacs)(void *cgx);

};



struct cgx {

	void __iomem		*reg_base;

	struct pci_dev		*pdev;

	u8			cgx_id;

	u8			lmac_count;

	struct lmac		*lmac_idmap[MAX_LMAC_PER_CGX];

	struct			work_struct cgx_cmd_work;

	struct			workqueue_struct *cgx_cmd_workq;

	struct list_head	cgx_list;

	u64			hw_features;

	struct mac_ops		*mac_ops;

	unsigned long		lmac_bmap; /* bitmap of enabled lmacs */

};



typedef struct cgx rpm_t;



/* Function Declarations */

void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val);

u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset);

struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx);

int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac);

int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id);

bool is_lmac_valid(struct cgx *cgx, int lmac_id);

struct mac_ops *rpm_get_mac_ops(void);



#endif /* LMAC_COMMON_H */