Commit 918a7a04 authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Borislav Petkov (AMD)
Browse files

x86/decompressor: Use standard calling convention for trampoline 



Update the trampoline code so its arguments are passed via RDI and RSI,
which matches the ordinary SysV calling convention for x86_64. This will
allow this code to be called directly from C.

Signed-off-by: default avatarArd Biesheuvel <ardb@kernel.org>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Acked-by: default avatarKirill A. Shutemov <kirill.shutemov@linux.intel.com>
Link: https://lore.kernel.org/r/20230807162720.545787-11-ardb@kernel.org
parent e8972a76

arch/x86/boot/compressed/head_64.S

+13 −14
Original line number Diff line number Diff line
@@ -444,9 +444,9 @@ SYM_CODE_START(startup_64) 
	movq	%r15, %rdi

	call	paging_prepare



	/* Save the trampoline address in RCX */

	movq	%rax, %rcx



	/* Pass the trampoline address and boolean flag as args #1 and #2 */

	movq	%rax, %rdi

	movq	%rdx, %rsi

	leaq	TRAMPOLINE_32BIT_CODE_OFFSET(%rax), %rax

	call	*%rax
@@ -531,11 +531,14 @@ SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated) 
SYM_FUNC_END(.Lrelocated)



/*

 * This is the 32-bit trampoline that will be copied over to low memory.

 * This is the 32-bit trampoline that will be copied over to low memory. It

 * will be called using the ordinary 64-bit calling convention from code

 * running in 64-bit mode.

 *

 * Return address is at the top of the stack (might be above 4G).

 * ECX contains the base address of the trampoline memory.

 * Non zero RDX means trampoline needs to enable 5-level paging.

 * The first argument (EDI) contains the 32-bit addressable base of the

 * trampoline memory. A non-zero second argument (ESI) means that the

 * trampoline needs to enable 5-level paging.

 */

SYM_CODE_START(trampoline_32bit_src)

	/*
@@ -582,7 +585,7 @@ SYM_CODE_START(trampoline_32bit_src) 
	movl	%eax, %cr0



	/* Check what paging mode we want to be in after the trampoline */

	testl	%edx, %edx

	testl	%esi, %esi

	jz	1f



	/* We want 5-level paging: don't touch CR3 if it already points to 5-level page tables */
@@ -597,21 +600,17 @@ SYM_CODE_START(trampoline_32bit_src) 
	jz	3f

2:

	/* Point CR3 to the trampoline's new top level page table */

	leal	TRAMPOLINE_32BIT_PGTABLE_OFFSET(%ecx), %eax

	leal	TRAMPOLINE_32BIT_PGTABLE_OFFSET(%edi), %eax

	movl	%eax, %cr3

3:

	/* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */

	pushl	%ecx

	pushl	%edx

	movl	$MSR_EFER, %ecx

	rdmsr

	btsl	$_EFER_LME, %eax

	/* Avoid writing EFER if no change was made (for TDX guest) */

	jc	1f

	wrmsr

1:	popl	%edx

	popl	%ecx



1:

#ifdef CONFIG_X86_MCE

	/*

	 * Preserve CR4.MCE if the kernel will enable #MC support.
@@ -628,7 +627,7 @@ SYM_CODE_START(trampoline_32bit_src) 


	/* Enable PAE and LA57 (if required) paging modes */

	orl	$X86_CR4_PAE, %eax

	testl	%edx, %edx

	testl	%esi, %esi

	jz	1f

	orl	$X86_CR4_LA57, %eax

1:

arch/x86/boot/compressed/pgtable.h

+1 −1
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ 


extern unsigned long *trampoline_32bit;



extern void trampoline_32bit_src(void *return_ptr);

extern void trampoline_32bit_src(void *trampoline, bool enable_5lvl);



#endif /* __ASSEMBLER__ */

#endif /* BOOT_COMPRESSED_PAGETABLE_H */