Commit 916b15fb authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'macb-ptp-minor-updates' 

Harini Katakam says:

====================
Macb PTP minor updates

- Enable PTP unicast
- Optimize HW timestamp reading
====================

Link: https://lore.kernel.org/r/20230411123712.11459-1-harini.katakam@amd.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents fb4be9a4 8c0d0fe0

drivers/net/ethernet/cadence/macb.h

+5 −1
Original line number Diff line number Diff line
@@ -95,6 +95,8 @@ 
#define GEM_SA4B		0x00A0 /* Specific4 Bottom */

#define GEM_SA4T		0x00A4 /* Specific4 Top */

#define GEM_WOL			0x00b8 /* Wake on LAN */

#define GEM_RXPTPUNI		0x00D4 /* PTP RX Unicast address */

#define GEM_TXPTPUNI		0x00D8 /* PTP TX Unicast address */

#define GEM_EFTSH		0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */

#define GEM_EFRSH		0x00ec /* PTP Event Frame Received Seconds Register 47:32 */

#define GEM_PEFTSH		0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
@@ -245,6 +247,8 @@ 
#define MACB_TZQ_OFFSET		12 /* Transmit zero quantum pause frame */

#define MACB_TZQ_SIZE		1

#define MACB_SRTSM_OFFSET	15 /* Store Receive Timestamp to Memory */

#define MACB_PTPUNI_OFFSET	20 /* PTP Unicast packet enable */

#define MACB_PTPUNI_SIZE	1

#define MACB_OSSMODE_OFFSET	24 /* Enable One Step Synchro Mode */

#define MACB_OSSMODE_SIZE	1

#define MACB_MIIONRGMII_OFFSET	28 /* MII Usage on RGMII Interface */
@@ -1363,7 +1367,7 @@ static inline bool macb_is_gem(struct macb *bp) 


static inline bool gem_has_ptp(struct macb *bp)

{

	return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);

	return IS_ENABLED(CONFIG_MACB_USE_HWSTAMP) && (bp->caps & MACB_CAPS_GEM_HAS_PTP);

}



/**

drivers/net/ethernet/cadence/macb_main.c

+13 −4
Original line number Diff line number Diff line
@@ -287,6 +287,11 @@ static void macb_set_hwaddr(struct macb *bp) 
	top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));

	macb_or_gem_writel(bp, SA1T, top);



	if (gem_has_ptp(bp)) {

		gem_writel(bp, RXPTPUNI, bottom);

		gem_writel(bp, TXPTPUNI, bottom);

	}



	/* Clear unused address register sets */

	macb_or_gem_writel(bp, SA2B, 0);

	macb_or_gem_writel(bp, SA2T, 0);
@@ -773,8 +778,12 @@ static void macb_mac_link_up(struct phylink_config *config, 


	spin_unlock_irqrestore(&bp->lock, flags);



	/* Enable Rx and Tx */

	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));

	/* Enable Rx and Tx; Enable PTP unicast */

	ctrl = macb_readl(bp, NCR);

	if (gem_has_ptp(bp))

		ctrl |= MACB_BIT(PTPUNI);



	macb_writel(bp, NCR, ctrl | MACB_BIT(RE) | MACB_BIT(TE));



	netif_tx_wake_all_queues(ndev);

}
@@ -3893,17 +3902,17 @@ static void macb_configure_caps(struct macb *bp, 
		dcfg = gem_readl(bp, DCFG2);

		if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)

			bp->caps |= MACB_CAPS_FIFO_MODE;

#ifdef CONFIG_MACB_USE_HWSTAMP

		if (gem_has_ptp(bp)) {

			if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))

				dev_err(&bp->pdev->dev,

					"GEM doesn't support hardware ptp.\n");

			else {

#ifdef CONFIG_MACB_USE_HWSTAMP

				bp->hw_dma_cap |= HW_DMA_CAP_PTP;

				bp->ptp_info = &gem_ptp_info;

#endif

			}

		}

#endif

	}



	dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);

drivers/net/ethernet/cadence/macb_ptp.c

+2 −2
Original line number Diff line number Diff line
@@ -258,6 +258,8 @@ static int gem_hw_timestamp(struct macb *bp, u32 dma_desc_ts_1, 
	 */

	gem_tsu_get_time(&bp->ptp_clock_info, &tsu, NULL);



	ts->tv_sec |= ((~GEM_DMA_SEC_MASK) & tsu.tv_sec);



	/* If the top bit is set in the timestamp,

	 * but not in 1588 timer, it has rolled over,

	 * so subtract max size
@@ -266,8 +268,6 @@ static int gem_hw_timestamp(struct macb *bp, u32 dma_desc_ts_1, 
	    !(tsu.tv_sec & (GEM_DMA_SEC_TOP >> 1)))

		ts->tv_sec -= GEM_DMA_SEC_TOP;



	ts->tv_sec += ((~GEM_DMA_SEC_MASK) & tsu.tv_sec);



	return 0;

}