Commit 91668ab7 authored by Athira Rajeev's avatar Athira Rajeev Committed by Michael Ellerman
Browse files

powerpc/perf: MMCR0 control for PMU registers under PMCC=00 



PowerISA v3.1 introduces new control bit (PMCCEXT) for restricting
access to group B PMU registers in problem state when
MMCR0 PMCC=0b00. In problem state and when MMCR0 PMCC=0b00,
setting the Monitor Mode Control Register bit 54 (MMCR0 PMCCEXT),
will restrict read permission on Group B Performance Monitor
Registers (SIER, SIAR, SDAR and MMCR1). When this bit is set to zero,
group B registers will be readable. In other platforms (like power9),
the older behaviour is retained where group B PMU SPRs are readable.

Patch adds support for MMCR0 PMCCEXT bit in power10 by enabling
this bit during boot and during the PMU event enable/disable callback
functions.

Signed-off-by: default avatarAthira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1606409684-1589-8-git-send-email-atrajeev@linux.vnet.ibm.com
parent 9a8ee526

arch/powerpc/include/asm/reg.h

+1 −0
Original line number Diff line number Diff line
@@ -864,6 +864,7 @@ 
#define   MMCR0_BHRBA	0x00200000UL /* BHRB Access allowed in userspace */

#define   MMCR0_EBE	0x00100000UL /* Event based branch enable */

#define   MMCR0_PMCC	0x000c0000UL /* PMC control */

#define   MMCR0_PMCCEXT	ASM_CONST(0x00000200) /* PMCCEXT control */

#define   MMCR0_PMCC_U6	0x00080000UL /* PMC1-6 are R/W by user (PR) */

#define   MMCR0_PMC1CE	0x00008000UL /* PMC1 count enable*/

#define   MMCR0_PMCjCE	ASM_CONST(0x00004000) /* PMCj count enable*/

arch/powerpc/kernel/cpu_setup_power.c

+1 −0
Original line number Diff line number Diff line
@@ -123,6 +123,7 @@ static void init_PMU_ISA31(void) 
{

	mtspr(SPRN_MMCR3, 0);

	mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);

	mtspr(SPRN_MMCR0, MMCR0_PMCCEXT);

}



/*

arch/powerpc/kernel/dt_cpu_ftrs.c

+1 −0
Original line number Diff line number Diff line
@@ -454,6 +454,7 @@ static void init_pmu_power10(void) 


	mtspr(SPRN_MMCR3, 0);

	mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);

	mtspr(SPRN_MMCR0, MMCR0_PMCCEXT);

}



static int __init feat_enable_pmu_power10(struct dt_cpu_feature *f)

arch/powerpc/perf/core-book3s.c

+4 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ static unsigned int freeze_events_kernel = MMCR0_FCS; 
#define SPRN_SIER3		0

#define MMCRA_SAMPLE_ENABLE	0

#define MMCRA_BHRB_DISABLE     0

#define MMCR0_PMCCEXT		0



static inline unsigned long perf_ip_adjust(struct pt_regs *regs)

{
@@ -1273,6 +1274,9 @@ static void power_pmu_disable(struct pmu *pmu) 
		val |= MMCR0_FC;

		val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |

			 MMCR0_FC56);

		/* Set mmcr0 PMCCEXT for p10 */

		if (ppmu->flags & PPMU_ARCH_31)

			val |= MMCR0_PMCCEXT;



		/*

		 * The barrier is to make sure the mtspr has been

arch/powerpc/perf/isa207-common.c

+8 −0
Original line number Diff line number Diff line
@@ -558,6 +558,14 @@ int isa207_compute_mmcr(u64 event[], int n_ev, 
	if (!(pmc_inuse & 0x60))

		mmcr->mmcr0 |= MMCR0_FC56;



	/*

	 * Set mmcr0 (PMCCEXT) for p10 which

	 * will restrict access to group B registers

	 * when MMCR0 PMCC=0b00.

	 */

	if (cpu_has_feature(CPU_FTR_ARCH_31))

		mmcr->mmcr0 |= MMCR0_PMCCEXT;



	mmcr->mmcr1 = mmcr1;

	mmcr->mmcra = mmcra;

	mmcr->mmcr2 = mmcr2;