Commit 915a6b99 authored by Zhang Zekun's avatar Zhang Zekun
Browse files

Revert "iommu/arm-smmu-v3: Add a SYNC command to avoid broken page table prefetch" 

hulk inclusion
category: bugfix
bugzilla: https://gitee.com/src-openeuler/kernel/issues/I913T5


CVE: NA

-----------------------------------

This reverts commit 8544c8e1.

Signed-off-by: default avatarZhang Zekun <zhangzekun11@huawei.com>
parent 30dc7d25

Documentation/arm64/silicon-errata.rst

+0 −2
Original line number Diff line number Diff line
@@ -156,8 +156,6 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | LINXICORE9100   | #162100125      | HISILICON_ERRATUM_162100125 |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | LINXICORE9100   | #162100602      | HISILICON_ERRATUM_162100602 |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | HIP09           | #162102203      | HISILICON_ERRATUM_162102203 |

+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |

arch/arm64/Kconfig

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@@ -836,19 +836,6 @@ config HISILICON_ERRATUM_162102203 


	  If unsure, say N.



config HISILICON_ERRATUM_162100602

	bool "Hisilicon erratum 162100602"

	depends on ARM_SMMU_V3

	default y

	help

	 On Hisilicon LINXICORE9100 cores, SMMU pagetable prefetch features may

	 prefetch and use a invalid PTE even the PTE is valid at that time. This

	 will cause the device trigger fake pagefaults. If the SMMU works in

	 terminate mode, transactions which occur fake pagefaults will be aborted,

	 and could result in unexpected errors.



	 If unsure, say Y.



config QCOM_FALKOR_ERRATUM_1003

	bool "Falkor E1003: Incorrect translation due to ASID change"

	default y

arch/arm64/configs/openeuler_defconfig

+0 −1
Original line number Diff line number Diff line
@@ -404,7 +404,6 @@ CONFIG_HISILICON_ERRATUM_1980005=y 
CONFIG_HISILICON_ERRATUM_162100801=y

CONFIG_HISILICON_ERRATUM_162100125=y

CONFIG_HISILICON_ERRATUM_162102203=y

CONFIG_HISILICON_ERRATUM_162100602=y

CONFIG_QCOM_FALKOR_ERRATUM_1003=y

CONFIG_QCOM_FALKOR_ERRATUM_1009=y

CONFIG_QCOM_QDF2400_ERRATUM_0065=y

arch/arm64/include/asm/cpucaps.h

+0 −1
Original line number Diff line number Diff line
@@ -81,7 +81,6 @@ 
#define ARM64_HAS_PBHA_STAGE2			73

#define ARM64_SME				74

#define ARM64_SME_FA64				75

#define ARM64_WORKAROUND_HISILICON_ERRATUM_162100602	76



#define ARM64_NCAPS				80

arch/arm64/kernel/cpu_errata.c

+0 −14
Original line number Diff line number Diff line
@@ -331,13 +331,6 @@ static const struct midr_range hisilicon_erratum_162100125_cpus[] = { 
};

#endif



#ifdef CONFIG_HISILICON_ERRATUM_162100602

static const struct midr_range hisilicon_erratum_162100602_cpus[] = {

	MIDR_REV(MIDR_HISI_LINXICORE9100, 0, 0),

	{},

};

#endif



#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003

static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {

	{
@@ -540,13 +533,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100125_cpus),

	},

#endif

#ifdef CONFIG_HISILICON_ERRATUM_162100602

	{

		.desc = "Hisilicon erratum 162100602",

		.capability = ARM64_WORKAROUND_HISILICON_ERRATUM_162100602,

		ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100602_cpus),

	},

#endif

#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003

	{

		.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",